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Technical Papers


Technical and applications information written and presented by Sigrity at  conferences and in publications devoted to electronic design strategies.

Sigrity customer technical papers can be found at Customer Success Stories.


Technical Papers
55. IBIS Presentation - Adapting AMI to Support Back-Channel Communications
- [IBIS Summit], June 8, 2011.

Proposed approach to increase the accuracy of channel simulations by including back-channel communications. The IBIS AMI modeling standard can be readily extended to support the new approach. This expands on the presentation given at the IBIS meeting in February, 2011.  Related Sigrity products:  SystemSI - Serial Link Analysis.

Document ~ Presentation
54. Analyzing Chips in a System Context
- [TSMC Open Innovation Platform], June 7, 2011.

Chip/system co-simulation can provide the only effective way to identify chip-level power delivery issues that don't show up until the die is incorporated in the system. This presentation describes techniques for assessing a range of designs including 3D IC and 2.5D projects which incorporate silicon interposers. Sigrity products that are part of the TSMC reference flow are highlighted: XcitePI, PowerSI, OrbitIO, XtractIM and OptimizePI.

Document ~ Presentation
53. Extending IBIS-AMI to Support Back-Channel Communications
- [IBIS Summit], February 3, 2011.

Chip/system co-simulation provides an important way  to identify and avoid chip-level issues that don't show up until the die is incorporated in the package. This approach enables system-level tradeoffs to maximize performance and/or reduce cost. The presentation also covers products that are included in TSMC reference flows along with new strategies for 3DIC and 2.5D IC designs that include Silicon Interposers. Related Sigrity products:  SystemSI - Serial Link Analysis.

Document ~ Presentation
52. Effect of Power Noise on Multi-Gigabit Serial Links
- [Customer Forum] October, 2010

This paper discusses the danger associated with treating designs as though they have ideal power characteristics.  This is particuarly true for multi-gigabit serial links.  Eye quality can be directly and significantly impacted by the presence of even relatively small noise currents.  This power delivery system noise may rival and surpass traditional signal-to-signal crosstalk as a main factor in serial link performance.  Related Sigrity products:  PowerSI and SystemSI - Serial Link Analysis.

Document ~ Paper (PDF Format)
51. Serial Link Engineering:  A Novel Jitter / Noise Metric to Qualify Channel Components
- [IEEE EMC] July 25, 2010

System interconnects are increasingly dominated by serial links.  Understanding the contribution of different system components to jitter and noise, and subsequently tuning those components, is the key to a successful design.  In this paper discusses an eye-area based normalized jitter and noise metric.  This approach can be consistently used for different data rates and to offer insight into various components to identify design risks.  Related Sigrity products: XcitePI, PowerSI, OrbitIO, XtractIM and OptimizePI.

Channel Designer.

Document ~ Paper (PDF Format)

50. IBIS-AMI Modeling Recommendations
- [European IBIS Summit], May 12, 2010.

This presentation describes the use of IBIS-AMI models in Serdes designs when Tx or Rx adaptive filtering is required as a convenient technique for designs that rely on static filtering.  IBIS-AMI model selection recommendations are made to avoid unnecessary complexity.  A run through of specific examples including Feed Forward Equalizer (FFE), Decision Feedback Equalizer (DFE), and an Advanced DFE is included.  Related Sigrity products:  Channel Designer.

Document ~ Presentation (PDF Format)
49. A Codesign Methodology for Efficient PoP Design
- [Wafer & Device Packaging and Interconnect], January / February issue, 2010.

Package-on-Package (PoP) implementations require early design planning to understand chip level IO pad ring options and to fully consider package interconnect options.  This is particularly important given the growing use of PoP designs and the desire to maximize the benefits offered by the compact form factor, configurability, and sourcing flexibility associated with PoP designs.  The article describes the benefits of understanding the complex IO implications for PoP and other multi-die designs.  Related Sigrity products: OrbitIO Planner.

Document ~ Article (Web Link)   (PDF Format)
48. Effectively Managing Signal and Power Delivery Impacts at the System Level
- [MEPTEC Seminar], February 25, 2010.

This presentation describes analysis techniques for system-level signal integrity, power integrity and design-stage EMC.  Design combinations can include packages and boards as well as chips.  Modeling implications are described along with the Model Connection Protocol approach to automate model connections.  For designs that include high-speed serial links, channel analysis is also discussed.  Related Sigrity products:  SPEED2000, PowerSI, OptimizePI  Channel Designer.

Document ~ Presentation (PDF Format)
47. IBIS-AMI and Statistical Analysis
- [DesignCon], February 3, 2010.

This paper describes key IBIS-AMI model concepts and the role this plays in the design of high-speed serial link designs.  Statistical analysis and time domain analysis techniques are also compared.  Sigrity products:  Channel Designer.

Document ~ Presentation (PDF Format)
46. Rapid Solution Techniques for Power Integrity - "Hybrid Solvers"
- [DesignCon], February 1, 2010.

This papers provides a reminder that current flows in loops.  Given this, meaningful assessment of a design's power delivery system of necessity must include a sufficient portion of system being analyzed.  The applicability of a range of solution techniques is covered with an emphasis on a hybrid solver approach.  The paper includes examples of designs with chip, package and board structures and shows applications including per-pin power and ground assessments, simultaneous switching noise studies and decoupling capacitor optimization.  Sigrity products:  OptimizePIXtractIM, PowerSI and SPEED2000 are also briefly discussed.

Document ~ Presentation (PDF Format)
45. Power Integrity Analysis Techniques to Get the Best System Performance at the Cheapest Cost
- [EDAPS2009], December 2, 2009.

This paper discusses what constitutes the best power plane performance with respect to both DC and AC.  Specific design types that benefit from analysis are discussed.  Ways to identify obscure but critical issues are explored as are available automation approaches.  Sigrity products:  PowerDC and OptimizePI.

Document ~ Presentation (PDF Format)
System-Level-SI-Oct-2009.png 44. Trends and Requirements for System-Level Design of Signal and Power Delivery
- [EPEP], October 18, 2009.

Robust system performance depends on effective management of signal and power delivery impacts at the system-level. This requires assessment of entire structures, efficient modeling and new techniques to address high-speed serial links. Accurate simulation requires both capacity and realistic consideration of the design’s power delivery network. An example relating to simultaneous switching noise is reviewed showing that unless signal and power integrity effects are considered together, risks are underestimated. Model generation is an important aspect in system-level studies and the high number of required connections is a complication. Solutions to address this complexity including Sigrity’s Model Connection Protocol (MCP) are discussed. The paper also outlines the challenges associated with designs that incorporate high-speed serial links where it is critical to manage a range of issues including jitter and overall Bit Error Rate (BER). Related Sigrity products: Channel Designer, SPEED2000 and XtractIM.

Document ~ Presentation (PDF Format)
Model-Connection-July-2009.png 43. Model Connection Protocols for Chip-Package-Board System-level Analysis
- [IBIS Summit, DAC], July 28, 2009.

Effective analysis of multi-level systems requires appropriate model abstraction. The need for pin-level as well as net level models applied to the same component adds complexity. New model connection protocols are emerging to simplify the challenge. This paper describes the overall trend and focuses on Sigrity's Model Connection Protocol (MCP). Sigrity's MCP is a publicly available approach. SPICE circuit header information is used and Sigritys MCP enables connection automation, speed and simplicity for model hook-up. Related Sigrity products: XtractIM.

Document ~ Presentation (PDF Format)
PoP-IO-Plan-May-2009.png 42. Concurrent Planning and Feasibility for Efficient Package-on-Package (PoP) Design
- [ECTC], May 26, 2009.

Package-on-Package (PoP) implementations have grown at a 40% compound annual growth rate. Compact form factor, configurability, test and sourcing flexibility are often mentioned as benefits. The key to efficient PoP devices is early design planning. A flow that supports assessment of package to package interface options is a central element to the flow as is early IO pad ring layout planning. The paper describes solutions for handling the complex IO implications for PoP and other multi-die designs. Related Sigrity products: OrbitIO Planner.

Document ~ Paper (PDF Format)        Document ~ Presentation (PDF Format)
Pad-Ring-May-2009.png 41. A Low-Cost Task Specific Solution for IO Pad-Ring and Package Net List Construction
- May 2009

Identifying downstream connectivity issues early enables improvement while options are cost effective. This paper describes typical flow and tool barriers to chip-to-package net list coordination. Sigrity's IC Net Planner is introduced. With a familiar spreadsheet paradigm and graphic visualization Net Planner facilitates rapid exploration of the solution space to reduce iterations and save time. Related Sigrity products: OrbitIO Planner.

Document ~ Paper (PDF Format)      
CoDesign-April-2009.png 40. Codesign Enables Rapid Development and High Performance
- [Solid State Technology], April 2009.

There are significant benefits associated with parallel chip/package/board codesign flows. Time to market savings are achieved through collaborative feedback and managing physical and electrical constraints across the design. The approach serves to greatly reduce the risk of design failure while at the same time enabling lower cost downstream implementation options. Related Sigrity products: XtractIM, PowerSI, XcitePI and OrbitIO Planner.

Document ~ Article (Web Link ...)
DC-Squeeze-Feb-2009.png 39. DC Design Squeeze
- [Printed Circuit Board Design and Fabrication], February 2009.

The voltage margins available for designers for DC have become extremely compressed. Multiple voltage domains and the impact of plane geometry irregularities exacerbate the issues. The article also discusses the ability to automatically pinpoint the best remote sense location to significantly impact DC margin. Design teams that effectively handle DC through the board and package design process are rewarded with additional confidence and margin to handle AC noise. A case study is described where a plane layer is removed safely in a design. Related Sigrity products: PowerDC.

Document ~ Article (Web Link ...) (PDF Format)
PCB-SI-Dec-2008.png 38. System IO Planning and Design Feasibility - Challenges and Solutions
- [DesignCon], February 4, 2009.

Industry trends and challenges associated with system IO planning are discussed in this paper. A new methodology is introduced that takes advantage of specially targeted software that is designed to handle chip, package and printed circuit board information. This new approach enables dynamic system IO planning across domains. Related Sigrity products: OrbitIO Planner.

Document ~ Paper (PDF Format)        Document ~ Presentation (PDF Format)
AMI-Models-Feb-2009.png 37. High-Speed Channel Designs - IBIS AMI Model Solution
- [DesignCon], February 3, 2009.

This presentation was given as part of a panel focused on channel design. It highlights the Algorithmic Modeling Interface (AMI) modeling standard which became available in August of 2008 with IBIS version 5. The standard allows chip developers to create executable black box models of transmitter and receiver behavior. With these models, systems developers can perform early architectural studies with confidence that the models they are using will be interoperable between suppliers. AMI transmitter and receiver models play a vital role in simulations of channel behavior as designs progress. Related Sigrity products: Channel Designer.

Document ~ Presentation (PDF Format)
SI-PI-EMI-Dec-2008.png 36. PCB Signal Integrity, Power Integrity and EMC Challenges
- [PCD&F], December 1, 2008.

SI, PI and EMC challenges are interrelated. This paper discusses the implications of coupling among traces as well as planes, vias and other design structures. Current loops and two terminal voltages make SI and PI issues virtually indistinguishable. Careful handling of SI and PI are also important to prevent EMC problems. This gives rise to the imperative for system-level analysis to analyze these combined challenges. Sigrity's hybrid solver approach provides needed accuracy with practical run times. Related Sigrity products: PowerSI and SPEED2000.

Document ~ Article (Web Link ...) (PDF Format)
3D-Packaging-Nov-2008.png 35. Addressing 3D Packaging Challenges
- November 24, 2008.

This paper focuses on issues that exist for those designing packages with stacked-die, package-on-package (PoP) and thru-silicon-via (TSV) implementations. These designs are growing in importance and require analysis approaches that account for 3D effects and physical implementation that assure complex structures such as cantilevered wirebond are designed for manufacturability. Early design planning is also key for these multi-die design where IO pad ring and package-to-package connectivity is of growing importance. Related Sigrity products: UPD, OrbitIO Planner and XtractIM .

Document ~ Paper (PDF Format)
AVP-Oct-2008.png 34. A Resonance-Free Power Delivery System Design Methodology Applying 3D Optimized Extended Adaptive Voltage Positioning.
- [EPEP Poster Session], October 27, 2008.

The paper describes the use of EAVP (Extended Adaptive Voltage Positioning) to select capacitors for the power delivery system of a system that included a six layer package with an eight layer board. An optimization is performed that considers both performance and cost that effectively results in a resonance-free design. Related Sigrity products: OptimizePI.

Document ~ Presentation (PDF Format)
Will-it-work-Sept-2008.png 33. Will it Work?
- [SOCcentral], September 2, 2008.

Without explicit design consideration of off-chip effects, it is difficult to assure a chip design will operate properly in a customers system. Design adjustments among the chip, package and even board physical domains can yield power integrity performance enhancement as well as cost savings, while avoiding the risk of chip failure when implemented in a system. Related Sigrity products: XcitePI, SPEED2000 and XtractIM

Document ~ Article (Web Link ...) (PDF Format)
Package Modeling June-2008.png 32. Electrical Modeling and Model Representations for Package Interconnects and Power Delivery Networks
- [IBIS Forum at DAC], June 10, 2008.

Presentation describing the range of modeling approaches and the impact on accuracy with recommendations for extensions to the IBIS standard. Related Sigrity products: XtractIM and PowerSI

Document ~ Presentation (PDF Format)
A-New-Power-Delivery-System.png 31. A New Power Delivery System Design Practice
- [PCB007], January 30, 2008.

Article comparing traditional PCB power delivery system design approaches to new methods which provide cost savings along with analytically assured performance. Related Sigrity products: OptimizePI

Document ~ Presentation (PDF Format)
Parallel-Processing-November 2007.png 30. Efficient Signal and Power Integrity Analysis Using Parallel Techniques
- [EPEP] Electrical Performance of Electronic Packaging, 2007.

Presentation describing parallel computing technology to use multi-processors in a singly system or across a network to increase simulation throughput. Related Sigrity products: PowerSI, OptimizePI and XtractIM

Document ~ Paper (PDF Format)       Document ~ Presentation (PDF Format)
IO-Planning-Sept-2007.png 29. Mastering the I/O Planning Puzzle
- [EETimes] September 24, 2007.

The key to system-wide IO planning is to achieve balance across all domains of the system so key decision criteria can be evaluated in the full system context to guide design decisions. Related Sigrity products: OrbitIO Planner

Document ~ Paper (PDF Format)
Signal and Power Integrity Aug 2007.png 28. Integrity Drives Successful Electronic Product Design
- [EETimes] August 27, 2007.

In this article Sigrity and Magma technical staff members describes important considerations for chip-package-board power and signal integrity analysis. Related products: PowerSI, XtractIM and OptimizePI.

Document ~ Paper (PDF Format)
Cost-Optimized-PDS-Mar-2007.png 27. Cost-Optimized PCB Power Integrity Design
- [PCD&M] Printed Circuit Design & Manufacture Magazine, March 2007.

New analysis tools measure the performance of the power delivery system and consider both cost and electrical performance resulting in a functional and cost-efficient design. Related Sigrity products: OptimizePI.

Document ~ Paper (HTML Format)


26. A Review of PCB-level Power Delivery System
   EE Times, Asia, China and Korea, May/June 2006

Improve power delivery system performance by understanding the fundamental issues in design, and doing extensive modeling and simulation of the entire PDS. Related Sigrity products: PowerSI and PowerDC.

Document ~ Paper (PDF Format, English)  Document ~ Paper (PDF Format, Chinese)

S-parameter-SSO-June-2005.png 25. Fundamentals of S-Parameter Modeling for Power Distribution System (PDS) and SSO Analysis
- [IBIS Summit] Anaheim, CA, June 2005.

Related Sigrity products: PowerSI and PowerDC.

Document ~ Presentation (PDF Format)
IR-Drop-April-2005.png 24. IR Drop in High-Speed IC Packages and PCBs
- [PCD&M] Printed Circuit Design & Manufacture Magazine, April 2005.

Neckdowns, low-weight copper and Swiss cheese effects are conspiring to wreak havoc on your high-speed design. Get the drop on them. Related Sigrity products: PowerDC.

Document ~ Paper (PDF Format)
Chip-Power-Integrity-Mar-20.png 23. On-Chip Power Integrity, Including Package Effects
- [SoC] SoCcentral Online Articles, March 14, 2005

On-chip power integrity effects and their influence on the entire power delivery system have become a major concern in the design of large and complex high-speed SoC designs. Today's extreme design challenges require a complete power-aware solution that encompasses the global effects of the entire power delivery system, including the realistic effects of the package and the PC board on the functional operation of the IC. Written by Dr. Fang and John Kane. Related Sigrity products: CoDesign Studio, XcitePI, SPEED2000.

Document ~ Paper (PDF Format)
IBIS-SSO-2005.png 22. An Initial Case Study for BIRD95: Enhancing IBIS for SSO Power Integration Simulation
- DesignCon, 2005.

This presentation is an overview on how BIRD95 can potentially help improve IBIS models. Related Sigrity products: SPEED2000.

Document ~ Presentation (PDF Format)
PDS-Decap-Oct-2004.png 21. A Fast Evaluation of Power Delivery System Input Impedance of Printed Circuit Boards with Decoupling Capacitors
- [EPEP] Electrical Performance of Electronic Packaging, 2004.

A fast power delivery system input impedance evaluation methodology for printed circuit board decoupling capacitor placement study is presented in this paper. Related Sigrity products: PowerSI and Broadband SPICE.

Document ~ Paper (PDF Format)       Document ~ Presentation (PPT Format)
Embedded-Passives-June-2004.png 20. Recent Developments in Polyimide-Based Planar Capacitor Laminates
- [ICEP] International Conference on Embedded Passives, June 2004.

This paper discusses performance and reliability data of both unfilled and ceramic-filled polyimide-based thin core laminates for use as embedded planar capacitor layers. A short overview of a simulation tool’s prediction of the impact of increasing the dielectric constant between power and ground will also be discussed. Related Sigrity products: PowerSI and SPEED2000.

Document ~ Paper (PDF Format)
EMC-with-SI-PI-April-2.png 19. Using Signal Integrity Analysis to Achieve EMC
- [PCD&M] Printed Circuit Design & Manufacturing Magazine, April 2004.

This paper discusses how some EMC engineers use signal integrity to help improve EMI performance and shorten testing times. Related Sigrity products: SPEED2000 and PowerSI.

Document ~ Article (PDF Format)
Power-Planes-Sept-2003.png 18. The Power of Planes - Low Impedance Power Delivery Over Broad Frequencies
- [PCD&M] Dr. Jiayuan Fang and Dr. Jin Zhao, Printed Circuit Design & Manufacturing Magazine, Sept. 2003. Related Sigrity products: PowerSI and SPEED2000.

This paper discusses low-impedance power delivery over broad frequencies, specifically how decoupling capacitors reduce impedances at low frequencies while removing resonances up to a few hundred MHz.

Document ~ Paper (PDF Format)
Signal-Propagation-2003.png 17. Measured and Simulated Signal Propagation Behavior on High Speed Nets of Large, High Dense, and Complex PCBs

The purpose of this paper is to evaluate, quantitatively, the influence of the individual parasitic parameter groups like on-board nets, chip packages, on-chip parameters on the total net performance of the simulation. Related Sigrity products: SPEED2000 and PowerSI.

Document ~ Paper (PDF Format)        Document ~ Presentation (PDF Format)
Decoupling-Oct-2001.png 16. Effective Decoupling Radius of Decoupling Capacitor
 - [epep2001_Chen] 

Decoupling capacitors on packages and printed circuits boards are often essential to reduce voltage fluctuations and maintain power and signal integrity. This paper presents a method for the evaluation of effectiveness of decoupling capacitors placed on package or board structures.  Related Sigrity products: PowerSI.

Document ~ Paper (PDF Format)        Document ~ Presentation (HTML Format)
Signal-Integrity-2001.png 15. Signal Integrity
 - [EMC-IEEE] Book Chapter, Engineering Electromagnetic Compatibility, Second Edition, IEEE Press and John Wiley & Sons, Inc.,  2001

In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced. Related Sigrity products: SPEED2000.

Document ~ Paper (PDF Format)  
20-H-Via-Shielding-2000.png 14. Effects of 20-H Rule and Shielding Vias on Electromagnetic Radiation From Printed Circuit Boards
 - [epep_2000]

This paper investigates the effects of the 20-H rule and shielding vias on the radiation from printed circuit boards. For the two-plane structure, 20-H rule yields much more radiation than the normal structure. For the multiple plane case, no significant change in radiation is found if the 20-H rule is applied to the internal planes. Also, the numerical result shows that the usage of shielding vias would cut down the radiation effectively. Related Sigrity products: SPEED2000.

Document ~ Paper (PDF Format)        Document ~ Presentation (HTML Format)
Modeling-PG-Oct-98.png 13. Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card
 - [epep98_amd] October 26, 1998

The electrical characteristics of power and ground supply of a PC microprocessor packaged in a BGA mounted on a PCB are studied with electromagnetic field analysis. The effects of decoupling capacitor types and locations is investigated to achieve the goals of low power and ground impedance and no or insignificant resonances inside the package. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)  
Power-Ground-Via-Oct-1998.png 12. Effects of Power/Ground Via Distribution on the Power/Ground Performance of C4/BGA Packages
 - [epep98_zhao] October 26, 1998

This paper studies the effects of the distribution of power and ground vias in BGA packages. Strategies that rely on vias concentrated in the core area is compared to uniform distribution. The performance is then evaluated in terms of resonance, impedance and effective inductance. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)  
Extraction-for-EM-Oct-1998.png 11. Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations
 - [epep98_moll] October 26, 1998

The extraction of circuit models for package power supply distribution systems from the results of full wave EM simulations is addressed. Both time and frequency domain optimizations are used for the extraction. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)  
EM-Coupling-May-1998.png 10. Validity of Mutual Inductor Model for Electromagnetic Coupling between Vias in Integrated-Circuit Packages and Printed Circuit Boards
 - [ectc98] May 25, 1998

A validity study of mutual inductor model for electromagnetic coupling between vias is presented in this paper. Comparisons are made between the mutual inductor model and full-wave field simulation. Limitations associated with the lowest resonant frequency are identified with electromagnetic simulation. Related Sigrity products: SPEED07

Document ~ Paper (PDF Format)  
Decoupling-Feb-1998.png 9. Where to Place Decoupling Capacitors ? -- Answer to a Problem Posted on SI-List
 - [reply] February 13, 1998

A discussion of the potential benefit associated with placing a capacitor at the site of a via even there are no adjacent components. Various electromagnetic simulations are performed to assess the variations of no decap, decap near via, decap near switching current source. Related Sigrity products: SPEED97

Document ~ Discussion (HTML Format)  
Shorting-Via-Arrays-Feb-199.png 8. Shorting Via Arrays for the Elimination of Package Resonance to Reduce Power Supply Noise in Multi-layered Area-Array IC Packages
 - [ipdi98] February 2, 1998

This paper presents full-wave electromagnetic field simulations on the effects of shorting via arrays for the reduction of power and ground noise. Properties of internal resonance in multi-layer packages are studied. Related Sigrity products: SPEED97

Document ~ Paper (HTML Format)  
EM-VIA-Coupling-Oct-1997.png 7. Significance of Electromagnetic Coupling Through Vias in Electronics Packaging
 - [epep97] October 27, 1997

The investigation on the relative significance of electromagnetic coupling between vias and parallel traces is presented in this paper. The study shows the coupling between vias can often be stronger than the coupling between traces. Related Sigrity products: SPEED97

Document ~ Paper (HTML Format)  
Input-Impedance-July-1997.png 6. The Facts about the Input Impedance of Power and Ground Planes
 - [inputimp] July 31, 1997

Power and ground planes may connect to the power supply at several locations. Moreover, a number of decoupling capacitors may be connected to the power and ground planes. Behavior at the low frequency limit is explored. Related Sigrity products: SPEED97

Document ~ Paper (HTML Format)  
Reduction-of-PG-Noise-Oct-1.png 5. Reduction of Power and Ground Noise Coupling in Mixed Signal Modules
 - [epep96] October, 1996

This paper covers the effectiveness of full-wave electromagnetic field simulation to identify and reduce power and ground noise coupling in mixed signal modules. Strategies associated with segmentation of the power and ground planes and proper placement of decoupling capacitors for the reduction of noise coupling are evaluated. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)        Document ~ Presentation (HTML Format)
Optimum-Decoupling-May-1996.png 4. Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation
 - [ectc96o] May 28, 1996

This paper presents an efficient signal integrity analysis technique for identifying voltage fluctuations on power/ground planes in complex packaging structures. Statistical noise voltage distributions can be used to assess the effectiveness of decoupling capacitor placement. The implications of value, number and location of decoupling capacitors is explored. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)  
SSO-May-1996.png 3. Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package
 - [ectc96m] May 28, 1996

The paper covers a laboratory experiment representing simultaneously switching circuits in a multi-reference plane design. Experimental data is compared to theoretical calculations and to simulated data from three modeling techniques of progressive complexity including lumped element, hybrid lumped element / transmission line and full wave solutions. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)
IBIS-May-1996.png 2. Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS
 - [ectc96ibis] May 28, 1996

Extraction and simulation of transient behavioral models of state transition of digital I/O buffers is introduced. A new approach is described which enables interconnect simulations with large numbers of simultaneously switching devices while maintaining accuracy compared to corresponding transistor level models. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)
Signal-Integrity-Oct-1995.png 1. A New Approach to Signal Integrity Analysis of High-Speed Packaging
 - [epep95] October 2, 1995

This paper describes an approach that simultaneously performs electromagnetic field simulation and circuit simulation. The electromagnetic field simulation algorithms leverage understanding of the unique geometric features of package and board structures to run two to four orders of magnitude faster than general-purpose electromagnetic simulators. The accuracy of simulated results are verified by lab measurements. Related Sigrity products: SPEED97

Document ~ Paper (PDF Format)


   1997-2012 Sigrity, Inc.
  Modified: October 31, 2012

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