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Sigrity Solutions

190+ Sigrity customers use our software for a variety of high performance IC package and printed circuit board applications addressing the needs of design analysis across silicon-package-board. IC package physical design software speeds the implementation of single die designs as well as SiP and PoP implementations.
Broadband-Model-Extraction    Broadband Model Extraction
Create broadband models for time domain circuit simulation with full-wave solver accuracy and models that are 2% of S-parameter model size.
Chip-Package-Board-Modeling Chip-Package-Board Modeling
Create ports for individual or grouped pins to achieve the desired level of abstraction when using models for either chip-centric or system-centric simulations.
Current-Density Current Density / IR Drop
Rapidly identify hot spots in structures including vias, traces, planes, bond wires and solder balls to avoid hard-to-detect failures.  Optimize sense line placement.
Co-Design Co-Design
Simultaneously simulate the entire chip power grid with the package / board in the time and frequency domain to find power integrity issues that are otherwise missed.
Decap-Optimization Decap Optimization
Assure power delivery system performance constraints are met while also targeting a decoupling scheme that is cost effective and conserves space.
Gain design stage visibility into potential hot spots with near and far-field radiation studies to compliment signal and power integrity analysis.
High-Speed-Interface-Analysis High-Speed Interface Analysis
Effectively deal with parallel (DDR) and serial (PCI-E) design challenges by analyzing system-wide behavior using SSO and channel studies.
IO-Planning IO Planning
Determine IO feasibility and assess implementation options across chip, package and board designs utilizing data from each of these environments.
Package-Layout Package Layout
Create manufacturing ready designs incorporating wirebond or flip-chip attachment using e-driven techniques to assure electrical constraints are met.
Power-Integrity Power Integrity
Assure robust power delivery system performance and mitigate the impact of coupling between planes, traces, vias and other structures.
RLGC-Extraction    RLCG Extraction
Rapidly generate IBIS or SPICE RLCG single-stage models (including Pi or T circuits) for selected nets or entire designs that include coupling effects.
Signal-Integrity    Signal Integrity
Analyze crosstalk, reflection, rise time degradation and related issues within a full system context to consider return path discontinuity with full wave accuracy.
SiP-Analysis-and-Design    SiP Analysis and Design
Extract models for the ever increasing range of multi-die implementation configurations, analyze the effect of noisy components and quickly create design layouts.
S-parameter-extraction-and-analysis    S-parameter Extraction and Analysis
Achieve the highest possible model accuracy and understand the most complex spatial relationships for complete package and board designs.
SPICE-Extraction-and-Analys    SPICE Extraction and Analysis
Generate models for use with SPICE compatible circuit simulators and enable practical design flows that accurately reflect power / ground plane effects.
Simulate ground noise propagation due to switching current under predicted and worst case conditions in the time or frequency domain for design improvement.

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  Modified: October 31, 2012

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