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Broadband Model Extraction
Create broadband models for time domain circuit simulation
with full-wave solver accuracy and models that are 2% of
S-parameter model size. |
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Chip-Package-Board Modeling
Group pins and create ports to achieve the desired level of
abstraction when using models for either chip-centric or
system-centric simulations. |
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Current Density
Rapidly identify hot spots in design structures including vias,
traces, planes, bond wires and solder balls to avoid hard-to-detect
field failures.
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Co-Design
Simultaneously simulate the entire chip power grid along with
package and board structures to identify power integrity issues that
are otherwise missed.
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Decap
Optimization
Assure power delivery system performance constraints are met while
also targeting a decoupling scheme that is cost effective and
conserves space.
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EMI /
EMC
Gain design stage visibility into potential hot spots with near and
far-field radiation studies to compliment signal and power integrity
analysis.
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High-Speed Interface Analysis
Effectively deal with DDR, SerDes and PCI-X challenges by analyzing
SSO, understanding power and ground structures and evaluating the
entire system in context.
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IO
Planning
Determine IO feasibility and implementation options across chip,
package and board designs utilizing data from each of these
environments. |
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Package
Layout
Create manufacturing ready designs incorporating wirebond or
flip-chip attachment using e-driven techniques to assure electrical
constraints are met.
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Power Integrity
Analytically assure power delivery system performance with studies
to determine the impact of coupling between diverse structures
including planes, traces and vias. |
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RLCG Extraction
Rapidly generate IBIS or SPICE RLCG single-stage models (including
Pi or T circuits) for selected nets or entire designs that include
coupling effects. |
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Signal Integrity
Analyze crosstalk, reflection, rise time degradation and related
issues within a full system context to consider return path
discontinuity with full wave accuracy. |
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SiP Analysis and Design
Extract models for the ever increasing range of multi-die
implementation configurations, analyze the effect of noisy
components and quickly create design layouts. |
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S-parameter Extraction and Analysis
Achieve the highest possible model accuracy and understand the most
complex spatial relationships for complete package and board
designs. |
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SPICE Extraction and Analysis
Generate models for use with SPICE compatible circuit simulators and enable
practical design flows that accurately reflect power / ground plane effects. |
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SSO / SSN
Simulate ground noise propagation due switching current under
predicted and worst case conditions in the time or frequency domain
to create targeted improvements. |
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