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| Our Customers |
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Sigrity customers include worldwide, leading companies in
diverse technology markets, including computer, semiconductor, graphics,
networking, communications, and consumer electronics. Our customers include
the worlds major electronic companies such as IBM, NEC, HP, TI, Infineon, Micron, Altera, Xilinx, ATI, NVIDIA, Cisco, Broadcom, Motorola, Sony, Samsung,
Toshiba and many more.
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| Customer Success Stories |
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38. |
An Optimized Cost / Performance Power Delivery System Design Using OptimizePI
-- Paul Chu - Inventec; May 2008
Presentation (PDF Format)
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37. |
Power Integrity in System Design
-- Skipper Liang - Flextronics; May 2008
Presentation (PDF Format)
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36. |
Power Distribution System, Co-Simulation of Chip, Package and Board
-- Jimmy Hsu - VIA; May 2008
Presentation (PDF Format)
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35. |
How to Reduce EMI Using CAE
-- In-Ho Choi - LG Electronics; March 2008
Presentation (PDF Format)
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34. |
Application of Integral Analysis Technique to Determine Signal- and Power Integrity of Advanced Packages
-- Nebojsa Nenadovic, Ekkehard Miersch, Martin Versleijen, Sidina
Wane - NXP Semiconductor and EFM Consulting; EPEP October 2007
This paper and poster session covers the application of an integral analysis technique for determining Signal Integrity (SI) and Power Integrity (PI) of complex and advanced package solutions. A representative System-in-Package (SiP) product has been used for the study of analysis methodology, tools and flow.
Paper
(PDF Format)
Poster (PDF Format)
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33. |
Study of Simultaneous
Switching Noise Reduction for Microprocessor Packages by
Application of High-K MIM Decoupling Capacitors
-- Om P.
Mandhana, Hector Sanchez, Joshua Seigel and Jonathan Burnett -
Freescale Corp.;
DesignCon February 2007
This paper describes the effect of using
an on-die metal High-K metal-insulator decoupling capacitor
(on-die High-K MIM DECAP) in reducing simultaneous switching
noise (SSN) for microprocessor packages.
Paper
(PDF Format)
Presentation (PDF Format)
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32. |
Packaging a Supercomputer in
PCI Express Form Factor
-- Mark
Bailey, Greg Edlund, Bob Morse, Ankur Parel - IBM Corp.;
DesignCon February 2007
This paper looks at the trade-offs between
power, cooling and performance involved in packaging the
Cell Broadband Engine, multi-core graphics processor, and
associated bridge chip on a PCI ExpressTM
card together with large amounts of memory. In particular,
it examines AC and DC power distribution over twenty
domains, PCI Express compliance, and timing specification
for a DDR2 interface.
Paper
(PDF Format)
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31. |
Power Integrity Analysis of a
Microcontroller plus its Chip Package
-- Ekkehard
Miersch C EFM Consulting, Thomas Steinecke, Mehmet Goekcen C
Infineon Technologies; EMC Conference Zurich C Singapore
2006
Co-simulation of wire-bonded ICs plus chip
packages for power integrity analysis.
Paper
(PDF Format)
Presentation (PDF Format)
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| 30. |
Power Delivery Validation of Processor Front Side Bus
-- Mahadevan Suryakumar, Jiangqi He - Intel Corp.; ECTC
Conf. June 2005
This paper discusses the power delivery validation methodology of the processor Front Side Bus
that allows the user to input a stream of data into the I/O's to measure the power supply noise and the resulting dynamic
power fluctuation.
Paper
(PDF Format)
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| 29. |
Comparative Study on Effectiveness of On-Chip, On-Package, and
PCB Decoupling for Core Noise Reduction by Using Broadband Power Delivery Network Models
-- Om P. Mandhana - Freescale Semiconductor; ECTC
Conf. June 2005
This paper discusses the effectiveness of on-chip, on-package, and printed
circuit board decoupling capacitors used in the power delivery network of high performance
microprocessor systems for reducing the core power and ground noise over a wide frequency range.
Paper
(PDF Format)
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| 28. |
Joint Study of Simultaneous Switching Noise
and IO Return Current for CMOS FPGA Package
-- Hong Shi - Altera Corp.;
DesignCon2005
This paper presents a joint study of return current effect
and SSN with a focus on ways to minimize the impact through chip and package co-design.
Paper
(PDF Format)
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| 27. |
Power Integrity Analysis of a Microcontroller plus its Chip Package
-- Ekkehard Miersch, Thomas Steinecke, Mehmet Goekcen
- EFM Consulting, Infineon Technologies; EMC Compo 2005
The power integrity of the system chip plus chip package of a 32-bit microcontroller has been successfully analyzed by co-simulation of the microcontroller plus its BGA.
Paper
(PDF Format)
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| 26. |
Decoupling Capacitance Platform for Substrates,
Sockets, and Interposers
-- Josh G. Nickel, Joseph F. Rosenberger
- Silicon Bandwidth; DesignCon2005
Our solution to power integrity is a novel structural integration of
decoupling capacitance between the core power nets and ground to enhance core power delivery.
Paper
(PDF Format)
Presentation (PDF Format)
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| 25. |
Power Delivery Modeling and Design Methodology for a Programmable Logic Device Package
-- Anil Pannikkat, Jon Long - Altera Corp.;
EPEP Conference 2004
A power delivery modeling and design methodology for a programmable logic device package
is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been
analyzed by commercial available power integrity software and calibrated with measurements.
Design modifications have then been carried out for power delivery system improvement of the package for next generation products.
Paper
(PDF Format)
Presentation (PDF Format)
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| 24. |
Transient Current Extraction from Time Domain Voltage Measurement
-- Yaping Zhou, Ben Herberg - Freescale Semiconductor;
EPEP Conference 2004
An easy method to extract the current signature of a core power supply is suggested and used to obtain the
transient current during HRESET of a microprocessor system.
Paper
(PDF Format)
Presentation (PDF Format)
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| 23. |
Power Delivery System Performance Optimization of a Printed
Circuit Board with Multiple Microprocessors
-- Om P.
Mandhana - Motorola Corp.; ECTC Conf., June 2004
An efficient simulation and analysis methodology for evaluating power delivery
system of a printed circuit board, mounted with multiple microprocessors is presented in this paper.
Paper
(PDF Format)
Presentation (PDF Format)
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| 22. |
High Speed DDR Performance in 4 vs 6 Layer FCBGA Package Design
-- Edward Chan, Huabo Chen, and Chee Yee Chung -
NVIDIA Corp.; ECTC Conf., June 2004
This is a comparative study of the performance of 4-layer and 6-layer FCBGA packages
designed to support a high speed DDR1 interface.
Paper
(PDF Format)
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| 21. |
Simulation Study of Power Delivery Performance on Flip-Chip Substrate
Technology
-- Ramani Tatikola, Musawir
Chowdhury - Agere Systems; ECTC Conf., June 2004
The input impedance of finite utility plane structures is calculated accurately
from the simulated package resonance data using a commercial signal integrity tool.
Paper
(PDF Format)
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| 20. |
Impact and Modeling of Anti-Pad Array on Power Delivery Systems
-- Zhiping Yang,
Sergio Camerlo - CISCO Systems; EPEP Conf., Oct., 2003
The impact of anti-pad array on power and ground planes, especially at the area right under the BGA package, has been studied in
this paper. An effective modeling and simulation approach based on 3D field computation has been used to take into
account the anti-pad array effect. The simulation results match the measurement results. It has been found that the effect of anti-pad array on power
delivery system is considerable; therefore it cannot be ignored in the power
delivery system analysis and design for high-speed applications.
Paper
(PDF Format)
Presentation (PDF Format)
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| 19. |
Impact of High Impedance Mid-Frequency Noise on Power Delivery
-- Jennifer Tsai - Mindspeed Technologies;
EPEP Conf., Oct., 2003
In this paper, the core switching noise analysis of the power distribution system (PDS) for a signal
processor on a card is presented. SIGRITY's SPEED2000, a SPICE and full-wave based simulation tool, is used to study the
frequency and transient responses of the core switching noise. The correlation between the result in frequency
domain and time domain is discussed in detail. The frequency responses of the on-chip switching current and
package current are introduced to illustrate that the noise level caused by the high impedance of the PDSi s also
frequency dependent.
Paper
(PDF Format)
Presentation (PDF Format)
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| 18. |
A Design Methodology for The I/O Power Supply of Next Generation Packaging
-- Gang Ji, Tawfik Arabi, Greg Taylor, and Mark Beiley -
Intel Corp.; EPEP Conf., Oct. 2002
The method of three-dimensional I/O power modeling will be reviewed in detail based on the learning from the
previous one-dimensional and two-dimensional models. This paper will cover the latest development of next generation
microprocessor I/O power models and the adoption of a new three-dimensional modeling methodology to meet the
challenging design requirements of a high performance signal bus with short turn-around times. The paper also presents
a new technique of using damping resistors to attenuate the high frequency noise on the IO supply.
Paper
(PDF Format)
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| 17. |
Package and Chip Design Optimization for Mid-Frequency Power Distribution
-- Bernd Garben,
George A.Katopis, Wiren D. Becker - IBM; EPEP Conf., Oct.,
2002
In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by
simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the
effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I
ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been
analyzed. Conclusions are presented to optimize the chip and package design.
Paper
(PDF Format)
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| 16. |
Study of Package EMI Reduction for GHz Microprocessors
-- Jiangqi He, Dong
Zhong, Steven Yun Ji, Gang Ji, Yuan-Liang Li -
Intel Corp.; EPEP Conf., Oct., 2002
In order to reduce the emissions from the
package, it is necessary to include certain package design
features. Three different package designs are investigated
to study their relative efficiency in suppressing the
emissions.
Paper
(PDF Format)
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| 15. |
Frequency Dependencies of Power Noise
-- Bernd Garben, Roland Frech, Jochen Supper, and Michael F. McAllister;
IEEE Transactions On Advanced Packaging, May, 2002
In this paper, frequency dependencies of
delta-I noise caused by variations of the on-chip switching activity
have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of
coincidences with resonances of the power distribution system.
Paper
(PDF Format)
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| 14. |
Achieving 3.2 Gb/s, 400 MTS
AGTL+ IO Through Robust Power Delivery Design
With Minimal Package Size
-- Chee-Yee Chung, Weimin Shi and Alex
Waizman - Intel Corp.; DesignCon, Jan. 2002
This paper details the design of an optimized and robust IO power delivery network for the 400MTS(double pumped 200MHz), 3.2Gbytes/s,
AGTL+ Processor-Side Bus (PSB) that links the Intel MCH
chipset and the Intel® Pentium® 4 processor. The MCH package size is minimized through
power/ground BGA ball count reduction, while compensating the degraded power delivery through the
addition of on package decoupling capacitors. This optimized power delivery design is derived through
exploring the preferred current return path, and analyzing the power network behavior in both time and
frequency domain (using SPEED2000 simulations). Validation results in actual system environments show close correlation with
predictions.
Paper
(PDF Format)
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| 13. |
Bumpless
Build-Up Layer Packaging
-- S. N. Towle, H.
Braunisch, C. Hu, R. D. Emery, and G. J. Vandentop - Intel Corp.; Proceedings of ASME Int. Mech. Eng.
Congress and Exposition (IMECE), Nov. 2001
On October 8, 2001, Intel
announced that it had developed a new technology called BBUL
(Bumpless Build-Up Layer) packaging. This technology enables
higher performance, thinner and lighter packages, and lower
power consumption. BBUL is a key step in Intel's plan
to build processors with more than a billion transistors,
running at about 20 GHz, in the next few years. Higher
performance packages require complex thermal, power delivery
and signal integrity solutions. SPEED2000 has been
successfully used for the development of power delivery
system of BBUL.
Paper
(PDF Format)
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| 12. |
Mid-Frequency
Delta-I Noise Analysis of Complex Computer System Boards
with Multiprocessor Modules and Verification by Measurements
-- Bernd Garben - IBM Germany; IEEE Transactions On Advanced
Packaging, August 2001
Abstract—This paper
describes an efficient methodology for mid-frequency delta-I
noise analysis of the power distribution network of a
computer system. The method allows fast and accurate power
noise simulations with SPEED97 on highly complex packaging
structures. Simulation results for the mid-frequency power
noise amplitudes on module and board planes and dependencies
on decoupling capacitor parameters are presented. The
package model used for the simulations allow the
identification of the dominant resonant oscillations on the
power distribution system following a delta-I step and yield
the time response of the on-chip, on-module and on-board
decoupling capacitors. The simulation results have been
confirmed by measurements within 5%.
Paper
(PDF Format)
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| 11. |
Integrated
Modeling Methodology for Core and I/O Power Delivery
-- Kaladhar
Radhakrishnan, Yuan-Liang Li, and William P. Pinello - Intel Corp.;
ECTC Conf., May 2001
Traditionally core power
delivery and I/O signal analysis were performed separately
to analyze the performance of a microprocessor package. In
this paper, the authors describe a methodology for analyzing
core and I/O power delivery using the same integrated model -- made
possible by SPEED2000. They state, "Having an
integrated model allows us to study the noise induced on the
core power nets due to switching currents on the I/O nets
and vice-versa ... By including the entire package in the
simulation model, it is possible to account for package
resonances and via interactions."
Paper
(PDF Format) |
| 10. |
Distributed
Models for Multi-Terminal Capacitors – Using 2D Lossy
Transmission-Line Approach
-- Yuan-Liang
Li, Mark Elzinga, and Farzaneh Yahyaei-moayyed - Intel Corp.; ECTC
Conf., May 2001
As clock speeds increase into
the gigaHertz regime, the interaction between capacitors and
power/ground planes of a package on which they are mounted
becomes vitally important. A 3D distributed model, based on
SIGRITY's SPEED2000, is proposed to more accurately evaluate
the total loop inductance of a capacitor mounted on pads
over vias connected to power/ground planes.
Paper
(PDF Format)
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| 9. |
A
Simulation Study of Simultaneous Switching Noise
-- C. T.
Chen and Q. L. Chen - Intel Corp.; ECTC Conf.,
May 2001
This paper
details comprehensive studies, using SPEED2000, of
simultaneous switching noise (SSN) effects such as skew,
overshoot, ringing, and power and ground fluctuations for
two types of packages: OLGA and WBGA, with or without on-die
interconnection models, different on-die decoupling
capacitor values, etc.
Paper
(PDF Format)
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| 8. |
System-Level I/O Power Modeling
-- W.P. Pinello, PR Patel, Y.L. Li -
Intel Corp.; ISMA Conf., Nov. 2000
SPEED
for electrical characterization of electronic packages in a system-level environment. Modeling and simulation results show the capability of the method by demonstrating both power delivery and I/O signal integrity analysis in a unified environment. In addition to flexibility, the proposed method is capable of achieving accurate results in a fraction of the time as was previously required.
Paper
(PDF Format) |
| 7. |
Mid-Frequency
Delta-I Noise Simulation on Complex System Boards Using SPEED97
and Measurement Verifications
-- Bernd Garben - IBM Germany;
EPEP Conf., October 2000
Speed97 provides very fast and efficient
simulations of highly complex packaging structures during every system development phase. The simulation results
has been confirmed by measurements within 5%. "There is an excellent agreement, within 5%, between measured
and simulated noise amplitude for 210nF capacitance which yeilds identical oscillation period. The 14mV mid-frequency
noise amplitude was measured on the bottom board planes
below one MCM corner. The (Speed97) simulation yields exactly the same value."
Download
the presentation slides and the EPEP (Electrical
Performance of Electronic Packaging) conference paper to learn
more about how
other companies are using SPEED for their power/ground noise
analysis.
Paper
(PDF Format)
Presentation (PDF Format)
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| 6. |
Via and Return Path Discontinuity Impact on High Speed Digital Signal Quality
-- Qinglun Chen - Intel Corp.;
EPEP Conf., October 2000
Download
the paper and the presentation slides to learn more about how SPEED can be applied in system
timing simulation while return path discontinuities have to be
considered.
Paper
(PDF Format)
Presentation (HTML Format) |
| 5. |
Evaluating
HDI Technologies for High-Bandwidth Applications
--
Sam Beal - Alpine Microsystems; HDI, July 2000
This
article illustrates the use of SPEED in the design and
analysis of a very high density interconnect system.
Paper
(MS Word Format) |
| 4. |
Using An Electromagnetic Simulation Tool For Demonstrations
In A Course On Electronics Packaging
--
Harry Kroger - SUNY; InterPAK Conf., June 1999
This paper presents the experience of using an electromagnetic simulation tool, SPEED97, in a course at the University of
Maryland.
Paper
(PDF Format) |
| 3. |
Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card
--
Dennis Herrell - AMD; EPEP Conf., October 1998
Paper
(PDF Format) |
| 2. |
Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations
--
Francesc Moll; EPEP Conf. , October 1998
Paper
(PDF Format) |
| 1. |
Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package
--
Steven Rosser, Michael Kerr - IBM; Chi Shih Chang - SEMATECH;
Jiayuan Fang, Zhaoqing Chen, Yuzhe Chen - SUNY; ECTC Conf., October 1996
Paper
(PDF Format) |
