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Sigrity customers include worldwide, leading companies in diverse technology markets, including computer, semiconductor, graphics, networking, communications, and consumer electronics. 

Customer Success Stories
41. The Application of IBIS-AMI Model Cascaded Simulation for 10 Gigabit Repeater Serial Link Analysis
-- Zhengrong Xu, Luyu Ma - Huawei; Lee Sledjeski, Nate Unger - TI; Ken Willis, Haisan Wang - Sigrity; IBIS Summit November 2011

Repeaters are increasingly being used in high-speed SerDes channels. This paper describes the implications for simulation and technology solutions that are now available to handle the use of repeaters. An application example utilizing IBIS-AMI modeling techniques in the simulation of a 10G channel shows the new approach. Sigrity products referenced: SystemSI.

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AMI Simulation with Error Correction to Enhance BER Performance
-- Xiaoqing Dong, Geoffrey Zhang - Huawei Technologies; Adge Hawes - IBM; Kumar Keshavan, Ken Willis, Zhangmin Zhong - Sigrity, Inc.; DesignCon February 2011

Designers of high speed SerDes systems are challenged to lower the Bit Error Rate (BER) of their designs.  Early simulation can play a key role in assessing system feasibility and predicting performance margins.  When designs include SerDes IP from multiple suppliers, IBIS-AMI models provide the needed interoperability.  This paper discusses identification of marginal serial links that can bring down overall system performance and cases where BER is not met.  Error correction techniques for end-to-end analysis are also discussed. Sigrity products referenced: SystemSI - Serial Link Analysis.

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39. Package Electrical Characterization Dependent Power and Signal Integrity Simulation - Analysis of Microprocessor Systems
-- Om Mandhana - Freescale Semiconductor; DesignCon February 2011

Iterative package analysis flows are increasing in prominence for those seeking robust system level power and signal integrity assessments.  This approach requires accurate electrical characterization of packages and boards along with accurate models of microprocessor circuits.  This paper discusses design flow options and the factors to consider to maximize accuracy with practical simulation run times.  Sigrity products referenced:  PowerSI, Broadband SPICE and XtractIM.

Document ~ Paper (PDF Format)   Document ~ Presentation (PDF Format) 


Optimization for 10Gbps Serdes
-- Skipper Liang, Delta Networks, Inc.; Sigrity User Forum May 2010

There are immense challenges associated with the design of the system profiled in this paper which operates at 10.3125Gbps per lane and includes SerDes, XUAI and PCIe.  Pre- and post-layout analysis techniques are used to assess the board and associated connectors.  Alternate scenarios are considered for PCB materials, via options, connector choices, etc.  Rapid board-level frequency domain simulations enable S-parameter comparisons.  The results correlate well with 3D simulations.  Time domain simulations of the entire channel include AMI models of transmitter and receiver behavior.  Jitter and overall performance assessment is used to assure the design confirmed to specifications.  Sigrity products referenced: Channel Designer and PowerSI.

Document ~ Presentation (PDF Format) 
Freescale-July-2009.png 37. Application and Extraction of IC Package Electrical Models for Support of Power and Signal Integrity Analysis
-- Om P. Mandhana, John Burnett, Brad Brim, Sam Chitwood - Freescale, Inc. and Sigrity, Inc; DAC July 2009

Simulated system noise values differ greatly based on the type of package model used and the conditions under which the models are extracted. This DAC poster session material covers assessments showing that broadband multi-segment models predict power and signal integrity performance in a more realistic way than conventional models. This makes it important to select the appropriate package model type for the anticipated signal bandwidths. Sigrity products referenced: XtractIM.

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Freescale-July-2009.png 36. Predicting Deterministic Jitter on Copper Interconnect
-- Leon Wu - Flextronics; Sigrity User Forum June 2, 2009

The presentation discusses various forms of jitter and assesses the ability of a new channel analysis flow to determine bit error rate (BER). Simulation efficiency and accuracy were important considerations for the application which required simulation of 10e15 bits. S-parameter simulated data was correlated with VNA measurements. Sigrity products referenced: Channel Designer.

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Samsung-March-2009.png 35. Mobile Package Design and Simulations
-- Se-Ho You - Samsung Electronics; Sigrity User Forum April 21, 2009

The opportunity to improve package performance is significant for those with a well thought out design flow. This presentation describes analysis performed on a PoP design with the associated printed circuit board. SSO simulations were performed on the DDR design using S-parameter data for the design which includes a DDR memory interface. Efforts were made to understand and improve power delivery performance. Results included a 33% decrease in package inductance. Sigrity products referenced: PowerSI and Broadband SPICE.

Document ~ Presentation (PDF Format) 
Broadband-Methodology-Feb-2.png 34. Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High-Speed IO Design
-- Hsing-Chou Hsu, Jack Lin - Via Technologies, AzureWave Technologies and Sigrity, Inc; DesignCon February 2009

This paper covers characterization utilizing frequency domain impedance information to assess power delivery system coupling and the impact this has on simultaneous switching effects for adjacent IO cells. A new method for integrated simulation is discussed along with key enabling technologies that enable the linking of broadband network parameter (BNP) information for chips, packages and boards. The resulting simulations identify frequency dependent issues and support what-if assessment of decoupling strategies. Sigrity products referenced: PowerSI and XcitePI.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Time-and-Frequency-Feb-2009.png 33. Time and Frequency Analysis of Signal Noise as a Function of Power Noise and Vice Versa of a Microcontroller Plus its Packaging
-- Ekkehard Miersch, Mehmet Goekcen, Thomas Steinecke - Infineon Technologies and EFM Consulting; DesignCon February 2009

The paper covers strategies for the assessment of signal and power integrity effects in complex systems that include chip and system level structures. Methods to determine current signatures are discussed along with frequency and time domain co-simulation techniques. Simulation results enable accurate assessment of distributed on-chip and package level decoupling capacitor implementations. Simulation results are correlated with measured data. Sigrity products referenced: XcitePI, SPEED2000 and PowerSI.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
AzureWave-Oct-2008.png 32. Analysis of Entire Power Distribution System of Chip, Package and Board for High Speed IO
-- Hsing-Chou Hsu, Jack Lin - AzureWave Technologies and Sigrity, Inc; EPEP October 2008

Analysis issues and co-simulation techniques for chip, package and board designs are compared to traditional approaches. Electrical interactions are identified and compared based using the new flow. Total impedance along with simultaneous switching noise is discussed. Sigrity products referenced: XcitePI and PowerSI.

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CAE-PI-Flow.png 31. CAE Flow in the Development of Digital Equipment
-- Motochiko Okano - Toshiba Corporation; September 2008

This paper discusses an overall system level power integrity design flow and a specific approach that streamlines PCB decap optimization. The flow utilized a chip PDN model in system level simulations that assure performance compared to target impedance. Sigrity products referenced: OptimizePI and SPEED2000.

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Amkor-Lim 2 September-2008.png 30. Advanced Package Design
-- Ho-Jeong Lim - Amkor Technology; September 2008

This paper covers layout considerations and an e-driven flow for single and multi-die SiP packages. Important capabilities to simplify layout, assure electronic performance and generate models are discussed. Sigrity products referenced: UPD and XtractIM.

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Amkor-Lee-September-2008.png 29. MCP and 3D Package Design
-- Sang-Hyeon Lee - Amkor Technology, September 2008

This paper covers the need for advanced capabilities for package layout designers such as bond wire handling, routing and complex metal fill.  Sigrity products referenced: UPD.

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LG-May-2008.png 28. Low Cost DTV-SoC System Implementation Using Integrated Signal Integrity Analysis
-- Tai-Sik Yang, Yong-Seok Kang, Tae-Lim Song, Yun Ra, Seok-Soo Lee, Woo-Hyun PaiK C LG Electronics; EMC Asia-Pacific Symposium; May 2008

Analysis of signal integrity and power integrity is a vital part of ensuring successful DTV package and board designs. Delivering designs that offer both high performance and low cost implementations makes the challenge even more acute. The design flow profiled in the paper provided important performance insights before manufacturing and correlated very well with measured results.  Sigrity products referenced: SPEED2000.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Inventec-May-2008.png 27. An Optimized Cost / Performance Power Delivery System Design Using OptimizePI
-- Paul Chu - Inventec; May 2008

This paper describes the importance of power rail integrity for printed circuit board designs and the role of decoupling capacitors in managing self and transfer impedance.  Design flow specifics are discussed along with the results achieved which included identification of a design scheme that offered a better impedance profile at a lower cost. Results were verified in the time domain and measurements of power noise were made.  Sigrity products referenced: OptimizePI

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Flextronics-May-2008.png 26. Power Integrity in System Design
-- Skipper Liang - Flextronics; May 2008

Power integrity concepts are covered in this paper along the relationship between power and signal integrity.  DC and AC analysis flows are discussed along with the actions to resolve problems.  DC issues relating to IR drop and current density are illustrated.  AC design flow recommendations in the paper begin in the frequency domain for extraction and spatial distribution analysis and proceed to the time domain for confirmation that specifications for slew, overshoot and load are met.  Sigrity products referenced: PowerDC, PowerSI and SPEED2000.

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VIA-May-2008.png 25. Power Distribution System, Co-Simulation of Chip, Package and Board
-- Jimmy Hsu - VIA; May 2008

This paper suggests the need for a new co-simulation analysis flow to enable design adjustments among chip, package and board to positively impact power integrity and cost.  A chip centric analysis showed that co-simulation identified issues that could not be observed with analysis of the IC power delivery system alone.  Various on-chip decoupling strategies were assessed along with multiple package and board decap schemes. Sigrity's Broadband Network Paramer (BNP) format is mentioned as key enabling technology.  Sigrity products referenced: XcitePI, CoDesign Studio and PowerSI. .

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NXP-October-2007.png 24. Application of Integral Analysis Technique to Determine Signal- and Power Integrity of Advanced Packages
-- Nebojsa Nenadovic, Ekkehard Miersch, Martin Versleijen, Sidina Wane - NXP Semiconductor and EFM Consulting; EPEP October 2007

This paper and poster session covers the application of an integral analysis technique for determining Signal Integrity (SI) and Power Integrity (PI) of complex and advanced package solutions.  A representative System-in-Package (SiP) product has been used for the study of analysis methodology, tools and flow.  The importance of maximizing simulation speed and accuracy is discussed and results are correlated with measurements.  Sigrity products referenced: SPEED2000.

Document ~ Paper (PDF Format)    Document ~ Poster (PDF Format)
Freescale-February-2007.png 23. Study of Simultaneous Switching Noise Reduction for Microprocessor Packages by Application of High-K MIM Decoupling Capacitors
-- Om P. Mandhana, Hector Sanchez, Joshua Seigel and Jonathan Burnett - Freescale Corp.; DesignCon February 2007

This paper describes the effect of using an on-die metal High-K metal-insulator decoupling capacitor (on-die High-K MIM DECAP) in reducing simultaneous switching noise (SSN) for microprocessor packages.  DDR2 / DDR3 system level modeling and simulations are performed in both the time and frequency domain.  Studies of loop inductance, self and transfer impedance, peak noise are performed.  Voltages are assessed at the receiver and eye diagrams are used to review simultaneous switching.  Sigrity products referenced: PowerSI and SPEED2000.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
IBM-February-2007.png 22. Packaging a Supercomputer in PCI Express Form Factor
-- Mark Bailey, Greg Edlund, Bob Morse, Ankur Parel - IBM Corp.; DesignCon February 2007

This paper looks at the trade-offs between power, cooling and performance involved in packaging the Cell Broadband Engine, multi-core graphics processor, and associated bridge chip on a PCI ExpressTM card together with large amounts of memory. In particular, it examines AC and DC power distribution over twenty domains, PCI Express compliance, and timing specification for a DDR2 interface.  Simulation results were correlated to lab measurements.   Sigrity products referenced: PowerDC and PowerSI.

Document ~ Paper (PDF Format) 
Infineon-2006.png 21. Power Integrity Analysis of a Microcontroller plus its Chip Package
-- Ekkehard Miersch C EFM Consulting, Thomas Steinecke, Mehmet Goekcen C Infineon Technologies; EMC Conference Zurich C Singapore 2006

Co-simulation of wire-bonded ICs plus chip packages for power integrity analysis.  Power integrity and EMI issues were assessed with chip centric assessments that included co-simulation of package and board structures.  Electromagnetic interactions inside planar package structures identified issues that would not have been observable with chip analysis alone.  Simulated data was correlated with lab measurements.  Sigrity products referenced: XcitePI.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Freescale-June-2005.png 20. Comparative Study on Effectiveness of On-Chip, On-Package, and PCB Decoupling for Core Noise Reduction by Using Broadband Power Delivery Network Models
-- Om P. Mandhana - Freescale Semiconductor; ECTC Conf. June 2005

This paper discusses the effectiveness of on-chip, on-package, and printed circuit board decoupling capacitors used in the power delivery network of high performance microprocessor systems for reducing the core power and ground noise over a wide frequency range.   The design flow discussed includes frequency based analysis of Z-parameter data which is extracted and converted into compact SPICE compatible circuits for time domain simulations.   Sigrity products referenced: PowerSI and Broadband SPICE.

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Altera-January-2005.png 19. Joint Study of Simultaneous Switching Noise and IO Return Current for CMOS FPGA Package
-- Hong Shi - Altera Corp.; DesignCon2005

This paper presents a joint study of return current effect and SSN with a focus on ways to minimize the impact through chip and package co-design.  Sigrity products referenced: PowerSI and SPEED2000.

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Infineon-2005.png 18. Power Integrity Analysis of a Microcontroller plus its Chip Package
-- Ekkehard Miersch, Thomas Steinecke, Mehmet Goekcen - EFM Consulting, Infineon Technologies; EMC Compo 2005

The power integrity of the system chip plus chip package of a 32-bit microcontroller has been successfully analyzed by co-simulation of the microcontroller plus its BGA.  Sigrity products referenced: XcitePI, CoDesign Studio, SPEED2000.

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Silicon-Bandwidth-February-2005.png 17. Decoupling Capacitance Platform for Substrates, Sockets, and Interposers
-- Josh G. Nickel, Joseph F. Rosenberger - Silicon Bandwidth; DesignCon February 2005

The paper covers frequency and time domain analysis of IC package structures that include a Silicon Bandwidth developed structural decoupling capacitance.  The results of the assessment are used to under stand power delivery functionality.  Sigrity products referenced: PowerSI and SPEED2000.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Altera-2004.png 16. Power Delivery Modeling and Design Methodology for a Programmable Logic Device Package
-- Anil Pannikkat, Jon Long - Altera Corp.; EPEP Conference 2004

A power delivery modeling and design methodology for a programmable logic device package is presented in this paper. Both the DC IR drop and high frequency power ground input impedance have been analyzed by commercial available power integrity software and calibrated with measurements. Design modifications have then been carried out for power delivery system improvement of the package for next generation products.  Sigrity products referenced: PowerSI.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Freescale-2004.png 15. Transient Current Extraction from Time Domain Voltage Measurement
-- Yaping Zhou, Ben Herberg - Freescale Semiconductor; EPEP Conference 2004

An easy method to extract the current signature of a core power supply is suggested and used to obtain the transient current during HRESET of a microprocessor system.  Simulated results are highly correlated with lab measurements through gigahertz frequencies.  Sigrity products referenced: SPEED2000.

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Motorola-2004.png 14. Power Delivery System Performance Optimization of a Printed Circuit Board with Multiple Microprocessors
-- Om P. Mandhana - Motorola Corp.; ECTC Conf., June 2004

An efficient simulation and analysis methodology for evaluating power delivery system of a printed circuit board, mounted with multiple microprocessors is presented in this paper. Sigrity products referenced: SPEED2000 and PowerSI.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
nVidia-June-2004.png 13. High Speed DDR Performance in 4 vs 6 Layer FCBGA Package Design
-- Edward Chan, Huabo Chen, and Chee Yee Chung - NVIDIA Corp.; ECTC Conf., June 2004

This is a comparative study of the performance of 4-layer and 6-layer FCBGA packages designed to support a high speed DDR1 interface.  Simulations are correlated with VNA measurements.  Sigrity products referenced: PowerSI and Broadband SPICE.

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Agere-June-2004.png 12. Simulation Study of Power Delivery Performance on Flip-Chip Substrate Technology
-- Ramani Tatikola, Musawir Chowdhury - Agere Systems; ECTC Conf., June 2004

The input impedance of finite utility plane structures is calculated accurately from the simulated package resonance data using a commercial signal integrity tool.  Sigrity products referenced: PowerSI and SPEED2000.

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Cisco-October-2003.png 11. Impact and Modeling of Anti-Pad Array on Power Delivery Systems
-- Zhiping Yang, Sergio Camerlo - CISCO Systems; EPEP Conf., Oct., 2003

The impact of anti-pad array on power and ground planes, especially at the area right under the BGA package, has been studied in this paper. An effective modeling and simulation approach based on 3D field computation has been used to take into account the anti-pad array effect. The simulation results match the measurement results. It has been found that the effect of anti-pad array on power delivery system is considerable; therefore it cannot be ignored in the power delivery system analysis and design for high-speed applications.  Sigrity products referenced: SPEED2000.

Document ~ Paper (PDF Format)  Document ~ Presentation (PDF Format)
Mindspeed-October-2003.png 10. Impact of High Impedance Mid-Frequency Noise on Power Delivery
-- Jennifer Tsai - Mindspeed Technologies; EPEP Conf., Oct., 2003

In this paper, the core switching noise analysis of the power distribution system (PDS) for a signal processor on a card is presented. SIGRITY's SPEED2000, a SPICE and full-wave based simulation tool, is used to study the frequency and transient responses of the core switching noise. The correlation between the result in frequency domain and time domain is discussed in detail. The frequency responses of the on-chip switching current and package current are introduced to illustrate that the noise level caused by the high impedance of the PDSi s also frequency dependent.  Sigrity products referenced: SPEED2000.

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IBM-October-2002.png 9. Package and Chip Design Optimization for Mid-Frequency Power Distribution 
-- Bernd Garben, George A.Katopis, Wiren D. Becker - IBM; EPEP Conf., Oct., 2002

In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and package design.  Sigrity products referenced: SPEED2000.

Document ~ Paper (PDF Format) 
IBM-May-2002.png 8. Frequency Dependencies of Power Noise
-- Bernd Garben, Roland Frech, Jochen Supper, and Michael F. McAllister - IBM; IEEE Transactions On Advanced Packaging, May, 2002

In this paper, frequency dependencies of delta-I noise caused by variations of the on-chip switching activity have been analyzed by simulations for a complex computer system board with multi-chip module, especially the impact of coincidences with resonances of the power distribution system.  Sigrity products referenced: SPEED2000.

Document ~ Paper (PDF Format) 
IBM-August-2001.png 7. Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards with Multiprocessor Modules and Verification by Measurements
-- Bernd Garben - IBM Germany; IEEE Transactions On Advanced Packaging, August 2001

In this paper a methodology for mid-frequency delta-I noise analysis of a power distribution system is discussed.  The approach enabled identification of the dominant resonant oscillations on the power distribution and have been confirmed by measurements within 5%.  Sigrity products referenced: SPEED97.

Document ~ Paper (PDF Format) 
IBM-October-2000.png 6. Mid-Frequency Delta-I Noise Simulation on Complex System Boards Using SPEED97 and Measurement Verifications
-- Bernd Garben - IBM Germany; EPEP Conf., October 2000

A power/ground noise analysis simulation methodology shows correlation within 5% of measured results creating an efficient environment for analyzing complex package structures during every system development phase.  Sigrity products referenced: SPEED97

Document ~ Paper (PDF Format) Document ~ Presentation (PDF Format)

Alpine-July-2000.png 5. Evaluating HDI Technologies for High-Bandwidth Applications
-- Sam Beal - Alpine Microsystems; HDI, July 2000

Wide I/O busses and switching at high speeds require careful handling to avoid system performance problems.  Implications for a range of designs including SiP are discussed.  3D modeling of package board data is used to predict switching noise voltage vs. area and determine resonance over the frequencies of interest.  Sigrity products referenced: SPEED97

Document ~ Paper (MS Word Format) 
SUNY-June-1999.png 4. Using An Electromagnetic Simulation Tool For Demonstrations In A Course On Electronics Packaging
-- Harry Kroger - SUNY; InterPAK Conf., June 1999

This paper profiles a range of experiences utilizing electromagnetic simulation as part of coursework at the University of Maryland.  Crosstalk and signal integrity issues were emphasized with observation of coupling between structures.  Sigrity products referenced: SPEED97

Document ~ Paper (PDF Format)
AMD-October-1998.png 3. Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card 
-- Dennis Herrell - AMD; EPEP Conf., October 1998

The electrical characteristics of the power and ground supply of a PC microprocessor packaged in a BGA package mounted on a PCB are studied by dynamic electromagnetic field analysis.  The effects of decoupling capacitors of different types at various locations are investigated to achieve the objectives of low power and ground impedance and low resonance inside the package.  Sigrity products referenced: SPEED97

Document ~ Paper (PDF Format)
University-October-1998.png 2. Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations 
-- Francesc Moll; EPEP Conf. , October 1998

Full wave extraction of circuit models for package power supply distribution systems is discussed along with time and frequency domain optimizations.  Sigrity products referenced: SPEED97

Document ~ Paper (PDF Format)  
IBM-October-1996.png 1. Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package 
-- Steven Rosser, Michael Kerr - IBM; Chi Shih Chang - SEMATECH; Jiayuan Fang, Zhaoqing Chen, Yuzhe Chen - SUNY; ECTC Conf., October 1996

A series of experiments representing simultaneously switching circuits in a multi-reference package are described.  Simulations are used to assess variations in package configuration complexity.  The results of various simulation approaches are compared to theoretical calculations.  Sigrity products referenced: SPEED97

Document ~ Paper (PDF Format)


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  Modified: October 31, 2012

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