XcitePI^TM performs both frequency and time domain simulations to enable the best possible understanding of dynamic noise that can impact chip power integrity.  Analysis of the full-chip power grid can be done incorporating fully distributed package effects to determine the existence and severity of power integrity issues including those that only show up when a chip is designed into a system.  XcitePI facilitates effective design improvement with a range visualization options to show the impact of changes in capacitor locations along with changes to bump, pad and the power grid designs.  This helps design teams avoid costly late stage design respins.

	XcitePI Data Sheet in PDF Format
	XcitePI Applications:
	Performing dynamic noise simulation of the full-chip power grid. Understanding complex chip-package-board noise propagation. Simulating voltage noise in the time domain. Conducting frequency domain impedance analysis. Analyzing simultaneous switching noise (SSN). Evaluating packaging alternatives along with bump, ball and power grid options. Assessing decoupling capacitor implementations both on- and off-chip. Generating SPICE or multi-port S-parameter models.
	XcitePI Advantages:
	Fastest analysis to support even large designs such as processors. Flexible incorporation of package board models with user controlled abstraction levels. Only way to catch power integrity issues that arise when the chip is incorporated into a system. Highest accuracy available by including distributed system models. Both time and frequency domain simulation support is included. Full consideration of mutual inductance and capacitance for enhanced accuracy. Rapid what-if scenario support to enable targeted design improvements. Designed for chip-package-board co-design and use with Sigrity's CoDesign Studio. Fits well with popular IC, package, SiP and board design flows.
	Evaluation
	To learn more about XcitePI or to begin an evaluation, please contact us.