|
|
 |
|
|
|
|
|
SystemSI addresses the
challenges associated with high speed designs with comprehensive
chip-to-chip signal integrity analysis solutions. SystemSI is available in two
configurations. SystemSI - Parallel Bus Analysis targets
source synchronous designs. SystemSI - Serial Link Analysis
focuses on projects with SerDes channels. SystemSI includes a
block based schematic editor to make it easy to get started with very basic data. As design work
progresses, models are swapped in to reflect the detail of design
structures. SystemSI includes frequency domain, time domain
and statistical analysis methods to ensure robust parallel bus and
serial link interface implementations.
|
 |
 |
SystemSI Data Sheet in PDF format |
|
|
|
SystemSI - Parallel Bus
Analysis: |
|
A targeted solution for the end-to-end analysis
of source synchronous parallel interfaces such as designs with
DDRx memory. Pre-layout capabilities (including an
optional via wizard) enable work to begin with models which are
quickly generated and connected. As the design is refined, more
detailed models are swapped in to reflect actual hardware
behavior. Concurrent simulation accounts for the effects
of dielectric and conductor losses, reflections, inter-symbol
interference (ISI), crosstalk and simultaneous switching noise.
These simulations are able to fully account for impacts
associated with non-ideal power delivery system characteristics.
Graphical outputs and post-processing options give designers
insights that help enable rapid system improvements. |
|
SystemSI - Parallel Bus Analysis Datasheet in PDF format |
|
|
|
SystemSI - Serial Link
Analysis: |
|
An award-winning chip-to-chip analysis solution
focused on high-speed SerDes designs such as PCIe, Xaui,
Infiniband, SAS, SATA, USB, etc. Early assessments are
made using basic templates. Industry standard IBIS AMI
transmitter and receiver models are fully supported to enable simulations of
channel behavior for serial links with chips
from multiple suppliers. Chip model developers have access
to techniques to assist in model development. Models of
multiple packages, connectors and boards can be added to reflect
the entire channel. Simulations identify crosstalk issues
and show the effectiveness of chip level clock and data recovery
(CDR) techniques. Full channel simulations including millions of bits
of data confirm overall bit error rates (BER) to determine if
jitter and noise levels are within specified tolerances. |
|
SystemSI - Serial Link Analysis Datasheet in PDF format |
|
|
|
SystemSI Advantages: |
|
 |
Precise simulations
for designs at frequencies that range from DC to 10+ gigahertz |
|
Accurate handling of
non-ideal power delivery system influences on signal integrity which
can be the dominant cause of reliability problems |
|
Easy-to-use graphic
editor including an novel net-based, block-wise schematic editor |
|
Proven S-parameter
handling to ensure accurate system level time domain simulations |
|
Benefit from related
Sigrity tools that support model extraction, tuning, conversion and
hook-up |
|
SPICE subcircuit-based
modeling approach supporting common formats such as IBIS, HSPICE,
Touchstone, BNP and MCP |
|
|
|
|
Evaluation |
|
To learn more about SystemSI or to begin an evaluation, please
contact us.
|
|
|
|
|
|
|
|
|
|
|
SystemSI
Awards |
|
|
|
|
|
 |
|
|
PCD&F Magazine Recognized SystemSI - Parallel Bus Analysis with a New Product
Innovation Award |
|
|
|
|
|
 |
|
|
SystemSI - Serial Link Analysis (Channel Designer) was
selected as an EDN Hot Product for 2010 |
|
|
The IEC selected SystemSI - Serial Link Analysis (Channel Designer) as a DesignVision
Award Finalist |
|
|
|
|
|
PCD&F Magazine Recognized SystemSI - Serial Link Analysis (Channel Designer) with a New Product
Innovation Award |
|
 |
