Sigrity offers advanced software solutions for package physical design and for analyzing power integrity, signal integrity and EMC in chips, packages and printed circuit boards.  Over 170 companies utilize Sigrity products as part of industry standard design flows from Sigrity, Cadence, Mentor Graphics, Altium, Zuken and AutoCAD.

			OptimizePI Automated board and IC package decap optimization that considers both target impedance and cost.  The result is decap savings of 20 - 50% with equal or better performance.
			PowerDC Efficient and accurate IR drop analysis and DRC sign-off solution to rapidly identify ideal sense line location, voltage drops and current hot-spots for IC packages and printed circuit boards.
			XtractIM Fast IC package RLC extraction for IBIS and SPICE models from an entire single or multi-die package in a single pass.  Broadband models can be generated to maximize analytically assured accuracy.
			PowerSI Advanced signal and power integrity analysis including S-parameter extraction with visualization of spatial relationships for entire IC package and printed circuit board structures.
			Broadband SPICE Highly automated conversion capability that synthesizes SPICE compatible circuits from N-port network parameters enabling frequency data to be used in time domain simulations.
			SPEED2000 Groundbreaking solution for time domain electromagnetic simulation of an entire IC package or printed circuit board for comprehensive signal and power integrity analysis with a single tool.
			Channel Designer Highly accurate high-speed serial link analysis utilizing industry standard IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver models to predict bit error rate and enable robust channel design.
			CoDesign Studio Unique design environment that supports simultaneous simulation of complete chips and the entire package utilizing data from popular chip and package layout design flows. Identifies multi-domain power integrity issues.
			XcitePI Full-chip power integrity solution that takes into account the complete capacitive and inductive coupling between all conductors of the IC power grid along with package plane effects including time and frequency domain analysis options.
			OrbitIO Planner Vertically aware IO planning and connectivity solution that enables trade-offs of gate to board level connectivity using data from mainstream IC, package and printed circuit board tools.
			Unified Package Designer (UPD) Versatile eDriven IC package physical design environment supporting a broad range of package types including wirebond, flip-chip, leadframe, system-in-package (SiP) and package-on-package (PoP).
	Evaluation
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