Sigrity offers advanced software solutions for package physical design and for analyzing power integrity, signal integrity and EMC in chips, packages and printed circuit boards. Over 250 companies utilize Sigrity products as part of industry standard design flows from Sigrity, Cadence, Mentor Graphics, Altium, Zuken and AutoCAD.

			OptimizePI A highly automated board and IC package AC frequency analysis solution. Supports pre-and post-layout decap studies and identifies impedance issues. Decap implementations are optimized for performance and cost.
			PowerDC An efficient DC sign-off solution for IC package and PCB designs with electrical / thermal co-simulation to maximize accuracy. IR drop and current hot-spots are quickly pinpointed. Best remote sense locations are automatically found.
			XtractIM A fast IC package RLC extraction and assessment solution with an option to generate highly accurate broadband models. Supports a broad range of package types including BGA, SiP and leadframe designs.
			PowerSI An advanced signal integrity, power integrity and design-stage EMI solution. Supports S-parameter model extraction and provides robust frequency domain simulation for entire IC package and PCB designs.
			Broadband SPICE A combination of S-parameter checking, tuning and extraction capability to convert N-port network parameters to efficient SPICE compatible circuits that can be used in time domain simulations.
			T2B Transistor to Behavioral Model Conversion is an efficient way to create accurate models for SSO and other simulations. These models run an order of magnitude faster than the original transistor models.
			SPEED2000 A complete PCB/package layout based time domain EM simulation tool for signal integrity, power integrity and design-stage EMI analysis. It supports advanced layout checking for design sign-off and debug.
			SystemSI A comprehensive and automated signal integrity environment for the accurate assessment of high-speed chip-to-chip system designs. Ensures robust parallel bus and serial link interface implementations.
			XcitePI A full-chip power integrity solution targeting chip/system co-simulation applications. It supports early chip power planning, IO and core power model extraction and simulation in both time and frequency domains.
			OrbitIO Planner An IO planning co-design solution for rapid pad ring implementation in single/multi-die package configurations. Support for flip-chip and wirebond feasibility including RDL using standard data from IC, package and PCB tools.
			Unified Package Designer (UPD) A versatile analysis-driven package design environment supporting a broad range of wirebond, flip-chip and leadframe packages including single die BGAs and SiP implementations.
	Evaluation
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