OrbitIO Planner helps chip and packaging teams assess gate to board level connectivity in a single environment. This enables IO and device placement decisions to be made in a full system context. OrbitIO Planner is easily deployed in Synopsys, Cadence, and Magma IC design flows and offers support for the most popular package and board design tools. Unlike iterative and spreadsheet based approaches, OrbitIO Planner enables decisions to be made and refined with the best available data thus reducing errors, complexity, and cost.

	OrbitIO Planner Data Sheet in PDF format
	OrbitIO Planner Applications:
	Planning chip-package-board designs in a unified environment Making die pad and ball assignments in the full system context Determining design feasibility early by considering size, placement, stack-up, etc Planning complex IC packages with SiP, stacked, and PoP integration Evaluating wire bond feasibility during pad ring layout Simplifying flip chip IO for easier bump escape and RDL routing Optimizing pad ring layout for application specific packaging
	OrbitIO Planner Advantages:
	Dynamic interaction utilizing data from IC, package, and board tools Ability to eliminate cost and complexity associated with poor IO planning Utilizes data from popular IC, package, and board layout systems Powerful placement visualization and optimization capability Vertically aware environment supporting stacked, SiP, and PoP designs Comprehensive hierarchy management and multi-domain correlation Can be readily used by non-experts
	Evaluation
	To learn more about OrbitIO Planner or to begin an evaluation, please contact us.