OrbitIO Planner helps chip and packaging teams assess gate to board level connectivity in a single environment. This enables IO and device placement decisions to be made in a full system context. OrbitIO Planner is easily deployed in Synopsys, Cadence, and Magma IC design flows and offers support for the most popular package and board design tools. Unlike iterative and spreadsheet based approaches, OrbitIO Planner enables decisions to be made and refined with the best available data thus reducing errors, complexity, and cost.

OrbitIO Planner Data Sheet
 

	OrbitIO Planner Applications:
	Planning chip-package-board designs in a unified codesign environment Prototyping pad-ring and package for early feasibility assessment Validating wirebond feasibility during early design planning Planning multi-die IO for SiP, PoP, TSV, and stacked-die packages Determining flip-chip bump pattern and route feasibility Optimizing pad-ring layout for multiple package variants Influencing system designs from the top-down or bottom-up
	OrbitIO Planner Advantages:
	Eliminate cost and complexity by minimizing over-design Anticipate and avoid downstream issues with early design planning Visualize full interconnect hierarchy from gate level to PCB in a single tool Expedite planning by utilizing best-available or virtual design data Easily incorporate new design content and process incremental updates Quickly generate design abstractions in response to marketing requests Avoid the cost and limitations of proprietary or scripted solutions
	Evaluation
	To learn more about OrbitIO Planner or to begin an evaluation, please contact us.

Paper:  "A Low-Cost Task Specific Solution for IO Pad Ring and Package Net list Construction"
 

Paper:  "System IO Planning and Design Feasibility - Challenges and Solutions"