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Channel Designer addresses the challenges associated with high speed serial link designs. As speeds approach 10 gigabits a second and beyond, the need to assess bit error rate (BER) and overall channel performance is essential. Channel Designer includes a graphical schematic editor and comprehensive support of IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver models. Channel templates are provided for on-chip algorithms as well as for board, package and connector physical structures. Unparalleled simulation accuracy is enabled by effective S-parameter handling. 2D and 3D eye diagrams and bathtub curves are useful in determining BER and confirming jitter tolerance.
PowerSI Channel Designer Data Sheet in PDF format
pre / post layout electrical anaylysis; power and signal integrity

Channel Designer Applications:

Designing robust products that use multi-gigabit serial links (ex. PCIe, SATA, Xuai, Infiniband, USB)
Performing assessments at every design stage from feasibility through verification
Simulating with industry standard IBIS-AMI transmitter and receiver models
Analyzing designs that consist of a single net through or an entire multi-board bus
Identifying performance boundaries with automated sweeping of bus operating scenarios
Simulating entire HSPICE characterized channels with along with stimulus information to confirm channel performance
Determining BER with 2D and 3D eye diagrams and bathtub curves to ensure channel robustness
Confirming that equalization and clock data recovery enable desired data rates and physical layer implementations
pre / post layout electrical anaylysis; power and signal integrity

Channel Designer Advantages:

Precise simulations for designs over broad frequency ranges (DC to 10+ gigahertz)
Proven S-parameter handling to ensure accurate system level time domain simulations
Easy-to-use graphic channel capture including an novel net-based, block-wise schematic editor
Unique support for cascaded IBIS-AMI models to simplify creation, debug and use
Flexible and automated model hook-up with Sigrity's open Model Connection Protocol (MCP)
Advanced crosstalk analysis to combat jitter in 10+ gigabit a second designs
Short time to results with Sigrity provided generic Tx / Rx AMI models and channel templates
Supports all popular PCB and package layout data formats
Evaluate power and signal integrity tools Evaluation
To learn more about Channel Designer or to begin an evaluation, please contact us.

 

Papers and Articles

     
  Article:  "Swimming in the Channel - Signal integrity problems can come back to bite you if you're not careful"
 
 

Paper:  "IBIS-AMI and Statistical Analysis"
 

 

Paper:  "Effectively Managing Signal and Power Delivery at the System Level"
 

   

 

 

Channel Designer Awards

 




The IEC selected Channel Designer Planner as a DesignVision Award Finalist

   
 



PCD&F Magazine Recognizes Channel Designer with a New Product Innovation Award

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  Modified: June 20, 2010

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