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Channel Designer addresses the challenges
associated with high speed serial link designs. As speeds approach 10 gigabits a second
and beyond, the need to assess bit error rate (BER) and overall channel performance is
essential. Channel Designer includes a graphical schematic editor and comprehensive
support of IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver models.
Channel templates are provided for on-chip algorithms as well as for board, package and
connector physical structures. Unparalleled simulation accuracy is enabled by effective
S-parameter handling. 2D and 3D eye diagrams and bathtub curves are useful in determining
BER and confirming jitter tolerance.
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Channel
Designer Awards |
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The IEC selected Channel Designer Planner as a DesignVision
Award Finalist |
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PCD&F Magazine Recognizes Channel Designer with a New Product
Innovation Award |
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