Last week, I read with great interest in the message posted on SI-list by Lawrence, as well as the comments of Frank Yuan. The problem raised in Lawrences message is actually almost identical to one of our demo examples of our software tool - SPEED97. Lawrence is quite right that "a capacitor might be needed at that via site even through there are no components nearby." The current in that via is really the main source that generates the fluctuation of voltage between the power and the ground planes. Therefore, the most effective place to put the capacitor is that via site. In practice, one should also put capacitors elsewhere on the board to ensure steady power and ground supply throughout the board and to prevent resonance inside the board. To help understand the physics of what is happening, I used SPEED97 and made a full-wave animation of electromagnetic field propagation between the power and the ground planes. Good location for placing the decoupling capacitor is also demonstrated through the full-wave animation. I placed these animations together with some discussions on our web site (http://www.sigrity.com) for interested SI-listers.
February 13, 1998
> > Lawrence Butcher <lbutcher@parc.Eng.Sun.COM> wrote:
> > Imagine that I build a 4 layer board. Imagine that there were two
> > chips on it, labeled U1 and U2. Imagine that I route the board
> > strictly manhatten style. All horizontal wires are on top above the
> > ground plane, and all vertical wires are on the bottom below the power
> > plane.
> > _______________
> > | |
> > | U1 ------* |
> > | | |
> > | | |
> > | | |
> > | U2 |
> > |_____________|
> > Normally, I would put bypass caps under U1 and bypass caps under U2.
> > I would cosy them up so that there was minimum distance between the
> > caps and the power supply pins on the chip.
> > Consider the image currents running on the power and ground planes.
> > An image current will sit directly under each wire. But that current
> > will have a hard time following the wire through the via, because it
> > would have to hop from the ground plane to the power plane.
> > It seems clear that a capacitor might be needed at that via site to
> > give the current in one plane a chance to hop to the other. Even
> > though there are no components nearby.
> > Intuition rarely substitutes for calculation. Question: Is this true?
> > How much capacitance? How does that vary if there are 40 wires instead
> > of 1? How does the number change with frequency?
> Dr. Frank Yuan <email@example.com> replied:
> First, the image current on power or ground plane sit directly under the
> trace will run in opposite direction as the trace current. Therefore when
> U1 send trace current out, the image return current on the plane flow
> right back towards U1, and go through bypass caps under U1 to power plane.
> This is why bypass caps should be, as you said, very close to power/ground
> pins on the chip. Seems to me no capacitors are needed at the via site or all
> over the board just for return path. However, de-caps may be need evenly
> over the board to supress power/ground noises (SSN) on the planes.
> Again accurate calculation helps a lot in answer those questions. An
> simulation tool call AC_GRADE from Viewlogic (Formerly Quad Design)
> does just that in analyze power and ground planes and the effects of
> decoupling capacitors.
In fact, the via near the upper right Connor is the only via passing through both power and ground planes, and the switching current it carries will induce electromagnetic (EM) wave between power and ground planes. Therefore, the most critical place to place the decoupling capacitor would be close to that via. That means, if you have one decoupling capacitor to suppress the voltage fluctuations between the power and ground planes, placing it near that via will achieve better results than placing it anywhere else, in this case. The complete simulation results shown below will validate the intuition.
The test structure contains 4 metal layers, as shown in the figure below.
There are a signal layer at the top, one power plane, one ground plane, and a signal layer at the bottom. The planes are 10 cm by 10 cm. Each dielectric layer is 30 mil thick and has a dielectric constant of 4. There are two traces, "trace a" on the top signal layer and "trace b" on the bottom signal layer. The two traces are connected to each other through "via 2". A current source with a source resistor is connected to "trace a" and "via 1" which is between the top signal layer and the power plane. A termination resister, Rterm, is connected to "trace b" and "via 3" which connects the bottom signal layer and the ground plane. The current source and the source resistor here represent a 50mA driver. The waveform of the current source is a pulse that has a 300ps low-to-high transition, 300ps duration, and 300ps high-to-low transition.
Three cases were studied.
Case 1. No decap.
Case 2. Decap near via 2.
Case 3. Decap near the switching current source.
The decap used in case 2 and 3 is a 100nF one with series L of 50pH and series R of 10 mOhm. And the spacing between the two leads of the decap is 2mm. SPEED97 used a 50 by 50 mesh to discretize the power and ground plane to accommodate the two adjacent vias of the decap. 200 time step simulation, which is about 2ns transient response, was executed on SPEED97. In the batch mode of SPEED97, all three cases took about the same 0.6 second to complete 200 time steps of simulation. The 2500 node voltages on the 50 by 50 mesh, which represents the spatial noise voltage distribution between the power and the ground planes, were recorded and shown in the following graphs.
Case 1. No Decoupling Capacitor
In the following graph, the animated wave propagation is the actual voltage fluctuation between the power and ground planes during the transient response. You can clearly see when the signal reaches the via near the upper-right corner. The switching current induces EM wave propagating away from that via in the radial direction. When the wave reaches the edges of the board, it gets reflected, and causes resonance inside the power/ground plane structure. From this animation, you probably already know where should be the most effective place for decaps.
Case 2, Decap near the via
The decap was placed as shown in the following screen.
The following graph shows the spatial voltage bounces between the power and ground planes during the transient simulation. You can clearly identify the location of the placed decap. When the voltages bounce to a positive amplitude, the decap-placed area looks like a dent, whereas the voltages experience a negative swing, the decap area appears to be a small bump. The decap tries to maintain steady power and ground supply when fluctuations occurs.
Case 3. Decap near the switching current source
The decap was placed near the current source as shown in the following picture.
The spatial voltage distribution suggests the decap was not effective until the peak noise was generated and propagated to the decap location. That is why placing the decap near the via is more effective.
The peak noise voltage distributions (maximum voltage swing at each location on the power/ground plane during the simulation) for each case was recorded and plotted in the following diagram. The yellow curve, which represents the peak noise distribution for no decap case, shows that most part on the power/ground planes have 30 to 40 mV noise. The green curve, for decap at current source location, shows that with a 100nF decap, some area on the power/ground planes now have lower noise of around 25 mV. And the cyan curve, for decap at the via location, clearly shows better decoupling, since now most part of the power/ground planes have voltage fluctuations less than 25 mV.
This demonstration shows that, with proper simulation tools that are capable of performing efficient electromagnetic field analysis, effects of decoupling capacitors on packages and printed circuit broads can be evaluated. Such tools can guide design engineers determine the value, the number and the location of the capacitors to be placed. The noise voltage distributions can be used to assess the effectiveness of decoupling capacitor placement.
PS. One of the references of placing decoupling capacitors with EM field tools is the paper titled "Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation", published in 1996 ECTC conference proceedings. It is available for download in the PostScript format.
Y. Chen, Z. Chen, and J. Fang, "Optimum Placement of Decoupling Capacitors on Packages and Printed Circuit Boards Under the Guidance of Electromagnetic Field Simulation," 46th Electronic Components & Technology Conference, Conference Proc., pp. 756-760, May 28-31, 1996, Orlando, Florida.
Also, in recent studies, we found using via and decoupling capacitor arrays can effectively eliminate package resonance, and therefore significantly reduce the power and ground supply noise as well as potential EMI problems of packages and boards. Some of these studies can be found from the following paper. The PostScript format of the paper can also be downloaded.
Jiayuan Fang, Jin Zhao and Jingping Zhang, "Shorting Via Arrays for the Elimination of Package Resonance to Reduce Power Supply Noise in Multi-layered Area-Array IC Packages", 1998 IEEE Symposium on IC/Package Design Integration, February 2-3,1998, Santa Cruz, CA.
The placement of decoupling capacitors is one of the crucial issues to ensure signal integrity. If your signal integrity tools can not solve this problem timely and accurately, SPEED97 is the right choice for you!
Modified: October 31, 2012
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