Customer Success Stories Published Technical Papers and Presentations 1. Achieving 3.2 Gb/s, 400 MTS AGTL+ IO Through Robust Power Delivery Design With Minimal Package Size --by Chee-Yee Chung, Weimin Shi and Alex Waizman,  Intel Corp.; DesignCon 2002 - High Performance System Design Conference, Santa Clara, CA, Jan. 29/30, 2002. This paper details the design of an optimized and robust IO power delivery network for the 400MTS(double pumped 200MHz), 3.2Gbytes/s, AGTL+ Processor-Side Bus (PSB) that links the Intel MCH chipset and the Intel® Pentium® 4 processor. The MCH package size is minimized through power/ground BGA ball count reduction, while compensating the degraded power delivery through the addition of on package decoupling capacitors. This optimized power delivery design is derived through exploring the preferred current return path, and analyzing the power network behavior in both time and frequency domain (using SPEED2000 simulations). Validation results in actual system environments show close correlation with predictions. Paper (PDF Format)  2. Bumpless Build-Up Layer Packaging -- by S. N. Towle, H. Braunisch, C. Hu, R. D. Emery, and G. J.  Vandentop, Intel Corp., Proceedings of ASME Int. Mech. Eng. Congress and Exposition  (IMECE), New York, Nov. 11-16, 2001. On October 8, 2001, Intel announced that it had developed a new technology called BBUL (Bumpless Build-Up Layer) packaging. This technology enables higher performance, thinner and lighter packages, and lower power consumption.  BBUL is a key step in Intel's plan to build processors with more than a billion transistors, running at about 20 GHz, in the next few years.  Higher performance packages require complex thermal, power delivery and signal integrity solutions.  SPEED2000 has been successfully used for the development of power delivery system of BBUL.  Paper (PDF Format)  3. Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards with Multiprocessor Modules and Verification by Measurements -- by Bernd Garben, IBM Germany, IEEE Transactions On Advanced Packaging, August 2001 Abstract—This paper describes an efficient methodology for mid-frequency delta-I noise analysis of the power distribution network of a computer system. The method allows fast and accurate power noise simulations with SPEED97 on highly complex packaging structures. Simulation results for the mid-frequency power noise amplitudes on module and board planes and dependencies on decoupling capacitor parameters are presented. The package model used for the simulations allow the identification of the dominant resonant oscillations on the power distribution system following a delta-I step and yield the time response of the on-chip, on-module and on-board decoupling capacitors. The simulation results have been confirmed by measurements within 5%. Paper (PDF Format)  4. Integrated Modeling Methodology for Core and I/O Power Delivery -- Kaladhar Radhakrishnan, Yuan-Liang Li, and William P. Pinello, Intel, ECTC Conf., May 2001 Traditionally core power delivery and I/O signal analysis were performed separately to analyze the performance of a microprocessor package. In this paper, the authors describe a methodology for analyzing core and I/O power delivery using the same integrated model --made possible by SPEED2000. They state, "Having an integrated model allows us to study the noise induced on the core power nets due to switching currents on the I/O nets and vice-versa ... By including the entire package in the simulation model, it is possible to account for package resonances and via interactions." Paper (PDF Format)    5. Distributed Models for Multi-Terminal Capacitors – Using 2D Lossy Transmission-Line Approach -- Yuan-Liang Li, Mark Elzinga, and Farzaneh Yahyaei-moayyed; Intel, ECTC Conf., May 2001 As clock speeds increase into the gigaHertz regime, the interaction between capacitors and power/ground planes of a package on which they are mounted becomes vitally important. A 3D distributed model, based on SIGRITY's SPEED2000, is proposed to more accurately evaluate the total loop inductance of a capacitor mounted on pads over vias connected to power/ground planes. Paper (PDF Format)    6. A Simulation Study of Simultaneous Switching Noise   -- C. T. Chen and Q. L. Chen, Intel; Jin Zhao, Sigrity, ECTC Conf., May 2001 This paper details comprehensive studies, using SPEED2000, of simultaneous switching noise (SSN) effects such as skew, overshoot, ringing, and power and ground fluctuations for two types of packages: OLGA and WBGA, with or without on-die interconnection models, different on-die decoupling capacitor values, etc.  Paper (PDF Format)    7. System-Level I/O Power Modeling -- W.P. Pinello, PR Patel, Y.L. Li, Intel, ISMA Conf., November 2000 SPEED for electrical characterization of electronic packages in a system-level environment. Modeling and simulation results show the capability of the method by demonstrating both power delivery and I/O signal integrity analysis in a unified environment. In addition to flexibility, the proposed method is capable of achieving accurate results in a fraction of the time as was previously required. Paper (PDF Format)    8. Mid-Frequency Delta-I Noise Simulation on Complex System Boards Using SPEED97 and Measurement Verifications -- by Bernd Garben, IBM Germany, EPEP Conf., October 2000 Speed97 provides very fast and efficient simulations of highly complex packaging structures during every system development phase. The simulation results has been confirmed by measurements within 5%. "There is an excellent agreement, within 5%, between measured  and simulated noise amplitude for 210nF capacitance which yeilds identical oscillation period. The 14mV mid-frequency noise amplitude was measured on the bottom board planes below one MCM corner. The (Speed97) simulation yields exactly the same value." Download the presentation slides and the EPEP (Electrical Performance of Electronic Packaging) conference paper to learn more about how other companies are using SPEED for their power/ground noise analysis. Paper (PDF Format)        Presentation (PDF Format)  9. Via and Return Path Discontinuity Impact on High Speed Digital Signal Quality -- by Qinglun Chen, Intel, EPEP Conf., October 2000 Download the paper and the presentation slides to learn more about how SPEED can be applied in system timing simulation while return path discontinuities have to be considered.  Paper (PDF Format)        Presentation (HTML Format)  10. Evaluating HDI Technologies for High-Bandwidth Applications -- by Sam Beal, Alpine Microsystems, HDI, July 2000 This article illustrates the use of SPEED in the design and analysis of a very high density interconnect system. Paper (MS Word Format) 11. Using An Electromagnetic Simulation Tool For Demonstrations In A Course On Electronics Packaging -- by Harry Kroger, et al.  InterPAK Conf., June 1999 This paper presents the experience of using an electromagnetic simulation tool, SPEED97, in a course at the University of Maryland. Paper (PDF Format) 12. Modeling of the Electrical Performance of the Power and Ground Supply for a PC Microprocessor on a Card  -- by Sigrity and AMD, EPEP, October 1998 Paper (PDF Format)     13. Extraction of Equivalent Circuit Models of Package Power Supply Distribution Systems from Full Wave EM Field Simulations  -- by Francesc Moll, EPEP, October 1998 Paper (PDF Format)  14.   Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package  -- by IBM, ECTC, October 1996 Paper (PDF Format)