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Press Release

For Immediate Release

Sigrity's Unified Package Designer Adopted by STATS ChipPAC for Use in Design Centers Worldwide

New Version of Unified Package Designer Delivers Embedded Electrical Parameter Extractor, Enhanced High-Speed Constraints and DRC for Performance-Driven Package Design

SANTA CLARA, Calif., November 13, 2006 — Sigrity, Inc., the market leader in signal and power integrity software solutions, today announced that STATS ChipPAC Ltd., a leading independent semiconductor test and advanced packaging service provider, has adopted Unified Package Designer (UPD), solution for its design centers worldwide.  UPD will be used as part of its design services for single and multi-chip semiconductor packaging.

Version 6.1, the latest release of UPD, debuts an enhanced electrically aware design environment based on  Sigrity's industry-proven SpeedXP technology. Major new components include an embedded electrical parameter extractor for generating highly accurate parasitic models of wirebonds, traces, vias, pads and other components; an expanded electrical constraint set; electrically aware design rule checking; and enhanced parasitic reporting.

Using UPD, users now can define electrical constraints for timing, allowable coupling, target impedance, and parasitic thresholds, in addition to substrate and assembly-based constraints. According to Kwok Keung Szeto, Senior Manager of the Technology Division at STATS ChipPAC, "Having the embedded electrical parameter extractor and constraints integrated within a single tool enables our engineers to immediately verify compliance with performance objectives, and reduces the iterations of using separate tools. STATS ChipPAC fully supports Sigrity's commitment to continuously enhance UPD, and is benefiting significantly from the integration between the SpeedXP technology and UP."

Jiayuan Fang, president of Sigrity, added, "The 6.1 release fo UPD is the first of several that will incorporate new signal and power integrity analysis capabilities based on our SpeedXP technology. We are pleased that companies such as STATS ChipPAC, which are driven by customers to provide design services that can quickly and accurately address the electrically constrained content of their designs, now have a more convenient way to do this. Embedding our electrical parameter extractor into UPD provides a unique, easy-to-use solution that is well integrated and supported by a single company."

Availability

Unified Package Designer version 6.1 is available now. Details are available from Sigrity sales representatives.

About Sigrity

Sigrity, Inc., a privately held U.S. company incorporated in 1998, delivers advanced software solutions for package physical design and for analyzing power and signal integrity in chips, packages and printed circuit boards.  Sigrity’s patented electrical analysis methodologies run orders of magnitude faster than general-purpose electromagnetic tools, helping leading companies in the semiconductor, computer, graphics, communications and networking industries ensure high performance and reduce time to market.  The company is headquartered in Santa Clara, Calif., with a direct sales force and representatives worldwide.  For more information about how to ensure operational designs by using Sigrity’s package physical design and power and signal integrity analysis solutions, please visit:
http://www.sigrity.com .

 

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