Press Release
For
Immediate Release
NEC Adopts
Sigrity's Chip-Package CoDesign Solutions for Dynamic Power
Analysis
CoDesign Studio and XcitePI Solutions Chosen to
Identify Critical Package Effects and Prevent Costly Repairs
SANTA CLARA, Calif., February
27, 2006 — Sigrity, Inc., today announced that
NEC Corporation has adopted Sigrity's XcitePI and CoDesign
Studio solutions for power and integrity analysis of
NEC's next generation of supercomputer products. XcitePI
performs full-chip, dynamic simulation of the complete
power grid to determine the severity of on-chip power
integrity issues. CoDesign Studio is the only EDA
solution that simultaneously co-simulates the complete
chip and entire package in an integrated design
environment, identifying all distributed package effects
that impact the correct operation of the chip to insure
ICs work as expected when placed into actual packages.
Sigrity's unique chip-package co-design analysis
approach provides fast and accurate results, potentially
saving millions of dollars by preventing costly respins.
According to Takeshi Nishikawa,
general manager of the Computer Division at NEC Corporation,
"Electrical power modeling of our very complex chip and its
entire package is a very complex process, and we believe
that the package effects will have a significant impact on
the correct operation of the chip. Sigrity's CoDesign Studio
solution with XcitePI and SPEED2000 quickly and effectively
addresses our concerns in a comprehensive manner. It
identifies critical chip-package interactions during power
integrity analysis that we need to address in order to meet
our commitment to operational excellence."
Jiayuan Fang, president of Sigrity,
said, "We're pleased that NEC, like several other leading
electronic companies, is using CoDesign Studio and XcitePI
for fast and accurate full-system power analysis. This
solution set delivers comprehensive analysis of both the
chip and package effects to ensure correct design operation
and to help reduce expensive design iterations."
Simultaneous Chip-Package
Co-Simulation
Unlike other EDA tools, CoDesign
Studio, performs simultaneous chip-package co-simulation,
analyzing power integrity of the entire chip and package
power delivery system to quickly achieve accurate results.
It combines Sigrity's SPEED2000 solution, the industry's
defacto standard for electrical analysis of packages, with
the company's XcitePI solution for IC power grid analysis.
CoDesign Studio takes into account the complete self and
mutual parasites of the chip and all electromagnetic
interactions within the package. Its' intelligent 'what-if'
analysis in the chip-package co-design environment provides
multiple design choices, including chip and package
decoupling capacitor selection and placement, flip-chip or
wirebond package selection, IC floor plan modification, and
C4 bump and IC power grid reconfiguration.
About
Sigrity
Sigrity, Inc., a privately held U.S.
company incorporated in 1998, delivers advanced software
solutions for package physical design and for analyzing
power and signal integrity in chips, packages and printed
circuit boards. Sigrity’s patented electrical analysis
methodologies run orders of magnitude faster than
general-purpose electromagnetic tools, helping leading
companies in the semiconductor, computer, graphics,
communications and networking industries ensure high
performance and reduce time to market. The company is
headquartered in Santa Clara, Calif., with direct sales and
global distribution through worldwide representatives. For
more information about how to ensure operational designs by
using Sigrity’s package physical design and power and signal
integrity analysis solutions, please visit:
http://www.sigrity.com
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