Sigrity's 11.1 Beta Release Information

November 11, 2011

The 11. beta release is available for immediate download for Windows and Linux customers. This release features a new product, Sigrity's T2B for Transistor to Behavioral Model Conversion along with improvements to each of our existing products.

OptimizePI now includes capabilities to optimize capacitor placement to remove resonance.
EMI and electromagnetic radiation can be significantly reduced with the printed circuit board design  improvements suggested by OptimizePI.

Users will see enhancements across all Sigrity products.  A summary of these capabilities is listed below.  This is a beta release and users are encouraged to provide feedback to Sigrity in advance of production availability.

ENHANCEMENT SUMMARY

Following is a partial feature summary.  11.1  beta software is available for electronic download at Sigrity's Customer Sign-In area (SPDNet). Primary user contacts have account user name and password information. Password retrieval is available at the site.

SpeedXP (11.1) Beta Release)

Overall SpeedXP capability:

• S-parameter model checks ... Designs are automatically parsed for all S-parameters that will be used in the simulation. A report is generated that alerts users to potential S-parameter data quality issues.

• Overall improvements ... "Special voids" can now be handled on a layer-by-layer basis. Various improvements have been made for shape processing, the net manager and the pad stack editor.

SPEED2000 capability:

• Signal integrity metric checking ... Set-up and post-processing is streamlined for serial channels and memory buses.

• Greater speed and capacity ... Improvements in memory handling, sparse matrix filling efficiency and multi-threading support.

• Enhanced accuracy ... Improved S-parameter handling and W-element support.

PowerSI capability:

Improvements to PowerSI overall capabilities in this beta release:

• Incorporating selected 3D results in PowerSI simulations ... Users with the PowerSI 3D FEM option can now perform a 3D analysis on a critical net and back-annotate the result into the overall PowerSI simulation.
   

• Geometry processing enhancements ... improved handling of both shap-to-trace intersections and vias near shape edges as well as a new shape cleanup process all better capture design intent for more accurate simulations.
   

• Reporting improvements ... Additional outputs and post-processing options.

     Improvements to PowerSI 3D FEM in this beta release:

• Automated coaxial port generation ... Saving users time in set-up of simulations of flip-chip design packages.

• Modeling of large planes ... Users are able to specify non-rectangular, conformally-shaped outer boxes rather than the default shape.

• Leadframe ex of large planes ... Users are able to specify non-rectangular, conformally-shaped outer boxes rather than the default shape.

Broadband SPICE capability:

• Additional capability to handle large cases ... Loading time is reduced and memory utilization has been improved.

• Refinement of passivity enforcement ... Significant enhancement with this release.

• Flow and checking improvements ... New capability for time domain model checking, a combined workflow for TD/FD model checking, plus additional tuning and extraction options.

T2B capability:

             Note:  This is the first SpeedXP release to formally include the new T2B product. Transistor to Behavioral Model Conversion is an efficient way to create accurate models for SSO and other simulations. These models run an order of magnitude faster than the original transistor models while retaining a high degree of accuracy.

• Converting transistor driver models ... Automation to generate IBIS 3.2, 4.2 or 5.0 models as well as new Sigrity accuracy-enhanced models.

• Provide needed accuracy ... Models produced are verified vs the original transistor model with a built-in time domain simulation wizard.

• Support full bus simulations ... Works with flows that include Sigrity's SystemSI and SPEED2000. Also improves results accuracy in flows that utilize HSPICE.

• Makes co-simulation practical ... Dramatically improves chip/system co-simulation efficiency and capacity to support studies of broadband chip, package and board models.

PowerDC capability:

• Display enhancements ... New layout overlay plot, autoscaling adjustments when zoomed views and refined current vector plotting.

• Extended topology reporting ... The recently introduced topology report becomes even more valuable to users as a way to manage simulations.

• Port reuse ... Designs that have had ports set-up for AC simulations in either PowerSI or Optimize can proceed with simulation in PowerDC without going through this step again.

SystemSI (11.1 Beta)

     Improvements to SystemSI – Serial Link Analysis (formerly Channel Designer) in this beta release:

• Automatic termination of unused terminals ... Eliminates tedious work to manually terminate unused subcircuit terminals.

• Repeater simulation ... New capability has been added to simulate repeaters in IBIS-AMI format enabling cascading of multiple serial link channels.

• SFP+ Compliance kit enhancements ... Coverage is now included for cable assemblies.

     Improvements to SystemSI – Parallel Bus Analysis is a new Sigrity product capability with this release:

• Raw HSPICE waveform batch processing ... HSPICE "tr0" waveforms can be post-processed creating an HTML report with JEDEC DDR measurements.

• Frequency domain analysis ... S-parameters can be extracted and information is displayed graphically.

• Reporting improvements ... Additions include worst-case summary tables, power ripple and derating extrapolation. A new "delay report" shows interconnect delay and skew. Excel outputs are generated.

• Automation for BroadbandSPICE users ... It is easier to use BroadbandSPICE models and there is simplified connectivity via Model Connection Protocol (MCP).

             Note:  Via Wizard is a new add-on option available to SystemSI users with the 11.1 release. Coupled via structures can be rapidly produced by the Via Wizard. Focused Sigrity 3D FEM capability extracts S-parameters and populates the SystemSI block for inclusion in the simulation.

• Pre-layout via model generation... Rapidly produces detailed coupled via structures for inclusion in early studies to maximize accuracy.

• Post-layout via pattern extraction ... A focused workflow enables complex via patterns to be "snipped" out of existing layouts to produce detailed S-parameter models for use in SystemSI simulations..

OptimizePI (11.0 Beta)

             Note:  With this release the numbering and schedule for OptimizePI release is moving to greater synchronization with other Sigrity analysis products. Availability of new releases will continue to follow the SpeedXP release somewhat. With the 12.0 release the release will be parallel.

Improvements to OptimizePI with this release::

• EMI optimization ... New capabilities are added with this release to consider EMI effects in addition to the impedance, cost, and area.

XtractIM (11.1 Beta)

Improvements to XtractIM in the beta release which will follow the SpeedXP release by approximately one month:

• DC electrical assessment reporting  ... Users who also have a PowerDC license will have access to expanded DC information as part of a sign-off report for IC package designs..
• Expanded signal net performance assessment ... Support is now in place for multi-die packages.
• Pin-based extraction with non-local reference pins ... This supports chip design flows that rely on partial-inductance type package models.

XcitePI (5.0 Production)

Improvements to XcitePI in the most recent production release:

• Simplified user interface ... The XcitePI user interface takes on the check-list style flow approach of other Sigrity tools.  Enhancements are available for port selection and MCP connections.

• Increased capacity ... A hierarchical database supports additional performance and capacity in the GDS flow.

Unified Package Designer (11.0 Production)

Improvements to UPD in the most recent  release:

• Leadframe metal handling … Parametric definition of paddle and tie-bars combine with expanded editing options to streamline the flow and reduce the need of MCAD tools.

• Leadframe wirebond enhancements … Automatic placement of bondfingers along a guide independent of wirebond or die data.

• New high-speed design rule … The clearance of critical nets to pads on adjacent layers can now be easily checked.

Orbit IO (11.0 Production)

Improvements to OrbitIO in the most recent release:

• Extended IOview capability … Automated and rule-driven  IO pad ring construction now includes PG and bump cell insertion as part of the OrbitIO pad ring option.

• Interface reuse … Easily export IO pad ring interfaces including bump and cell insertion.

• Enhanced RDL routing … New interactive editing capability is provided in the FC feasibility option.  Compaction functionality has also been added to maximize area available for PG mesh.

• Bump pattern construction … Flexible support for regular and asymmetrical multiple pitch patterns is included with the FC feasibility option.  This capability includes the ability to export appropriate bump views to IC and package design tools.

• Die shrink support … Die data can now be imported at drawn scale with a shrink value applied to represent final scale using the FC feasibility option.  Die related changes will export at the drawn scale while package related bump data will export at final scale.