Sigrity's 11.0 Beta Release Information

April 26, 2011

The 11.0 beta release is available for immediate download for Windows and Linux customers. This release features several new products and improvements to each of our existing products.

New advanced checks in PowerSI and SPEED2000 make it easy to find impedance and coupling problems.  Plots are associated with 3D package and board structures.

Users will see enhancements across all Sigrity products.  A summary of these capabilities is listed below.  This is a beta release and users are encouraged to provide feedback to Sigrity in advance of production availability.

New products offered in this release are:

• SystemSI – Parallel Bus Analysis:  Focused solution for the assessment of DDRx and other interfaces.  Introduced as part of the SystemSI product family which now also includes Sigrity’s Channel Designer which is now “SystemSI – Serial Link Analysis”.  Stay tuned for Sigrity's formal product announcement on June 1, 2011.
• PowerSI  3D FEM Full-Wave Extraction Option:  New capability that shares a use model that compliments PowerSI to enable detailed assessment of structures such as via transitions and two layer boards.

Users will see enhancements across all Sigrity products.  A summary of these capabilities is listed below.  This is a beta release and users are encouraged to provide feedback to Sigrity in advance of production availability.

ENHANCEMENT SUMMARY

Following is a partial feature summary.  11.0  beta software is available for electronic download at Sigrity's Customer Sign-In area (SPDNet). Primary user contacts have account user name and password information. Password retrieval is available at the site. Translator licensing changes with this release. While older versions will continue to work, you may want to have your license file updated to reflect the CAD systems you use when analyzing data with SPEED2000, PowerSI, PowerDC, OptimizePI and XtractIM. Your Sigrity representative can assist you with this.

SpeedXP (11.0) Beta Release)

Overall SpeedXP capability:

• Decap library support … Decap models can now be quickly assigned from selected decap vendor libraries that are provided with the SpeedXP installation.

• Improved merge functions with MCP … Simplifies simulations where multiple physical databases are to be simulated.

SPEED2000 capability:

• PCB / Package layout SSO checking … Simplifies the identification of crosstalk with time domain analysis that supports user-selectable checking groups and reports that confirm results.

• PCB / Package trace impedance / coupling checking … This release includes advanced checks including trace reference discontinuities, traces over voids, etc.  Interactive checks are also available for detailed review and report is provided.

• TDR / TDT workflow improvements … Simulations are now easier to setup and run.  A TDR / TDT simulation summary report is also available.

• Support for IBIS BIRD98 … All IBIS 5.0 power aware capabilities are now included enabling simulations to capture power noise generated at the chip level.

PowerSI capability:

• New 3D FEM Full-Wave extraction option … New and separately priced product capability for detailed analysis of specific package and board structures such as via transitions and two layer boards lacking reference planes.

• Multi-threading support ... Additional matrix pre-processing is now supported to accelerate simulation throughput.

• Performance enhancements … This release includes several speed improvements including the reuse of trace library information and near field results.

• PCB / Package trace impedance / coupling checking … This release includes advanced checks including trace reference discontinuities, traces over voids, etc.  Interactive checks are also available for detailed review and report is provided.

• Reference plane handling … Greater ability to accurately assess reference planes even when detail is missing.

Broadband SPICE capability:

• Additional S-parameter tuning options … Users are able to control elements such as the removal of low frequency points and extrapolations related to both low and high frequencies.  Time domain verification is also provided to confirm overall S-parameter quality.

• Greater SPICE model extraction accuracy … New patent-pending capability supports adaptive port impedance for SPICE model extraction to significantly improve accuracy.

• S-parameter reciprocity checking … This new check was added with this release and existing S-parameter checking options were also enhanced.

• New workflow … Users can easily follow recommended steps for checking, tuning and extracting S-parameter models.

• Faster file loading … S-parameter loading is significantly faster with this release.

PowerDC capability:

• Reporting enhancements … New block diagram functionality has been added to PowerDC with this release with voltage and current information seen in this context.  Users can also capture images of specific design regions and have the HTML report provide related specifics.

• Pin location effectiveness … A new easy to set up workflow shows which pins are not effective due to high resistance from the VRM.  Information is plotted to give an intuitive understanding and a tabular report shows additional detail.

• Pin IRdrop plot … Newly available simulation results images show the IRdrop from the VRM to each sink pin with a color scale to enable a rapid understanding of potential issues.

• Thermal enhancements for EEs … With this release thermal co-simulation is now incorporated in the core PowerDC application.  Stack-up materials choices are made by default if the user does not have ready access to detailed materials information.

Sigrity translation capability

• ODB++ to SPD ... New import translation offering that imports layout data from what has emerged as an industry standard format. This will be particularly valuable to Mentor Expedition customers but can simplify the transfer of design data from any CAD tool that supports ODB++ output.
• SPDLinks User Interface ... Improvements include easy-to-use pattern matching on the select net UI.
• Licensing change ... Translators are now individually licensed for use with the Sigrity products that utilize them (SPEED2000, PowerSI, PowerDC, OptimizePI and XtractIM).

Channel Designer capability (see SystemSI) and watch for our announcement on June 1, 2011.

SystemSI (11.0 Beta)

Sigrity’s Channel Designer product is moving into the new SystemSI product family.  It is now called SystemSI – Serial Bus Analysis.  A new product, SystemSI – Parallel Bus Analysis is also being introduced with this release.

Improvements to SystemSI overall capabilities in this beta release:

• Results browser … Loading and recall of previous run result straight-forward in this results browser which is shared amongst SystemSI products.

• Auto-termination … Unused terminals in large subcircuits are now automatically terminated based on user specifications for signal, ground, and power terminals.

• Via Wizard … Users can quickly define coupled via models in a graphical GUI and solve them quickly with Sigrity’s PowerSI 3D-FEM Full-Wave Extraction Option to produce S-parameter models.

Improvements to SystemSI – Serial Link Analysis (formerly Channel Designer) in this beta release:

• PCI Express Gen 3 compliance kit … New compliance kit follows the PCI Express Gen 3 standard, including IBIS-AMI models with back-channel support.

• TLine materials sweep … The Sweep Manager now supports the sweeping of TLine material properties such as permittivity and loss tangent.

• Crosstalk victim and stimuli sweep … The Sweep Manager now supports the sweeping of all receivers as well as the stimuli applied to aggressor transmitters.

SystemSI – Parallel Bus Analysis is a new Sigrity product capability with this release:

• Analyze high-speed source-synchronous designs … This new product provides focused capability to ensure timing margins and quality of DDRx interfaces can be comprehensively analyzed at the system-level.  Simulations include the effects of dielectric and conductor losses, reflections, ISI, crosstalk, and SSO.

• Automated measurement / report generation … Raw waveforms are automatically post-processed to take critical measurements and produce tabulated reports for:  over / undershoot, eye quality, setup / hold, and skew.

OptimizePI (11.0 Beta)

Improvements to OptimizePI in the beta release which will follow the SpeedXP release:

• EMI optimization ... New capabilities are added with this release to consider EMI effects in addition to the impedance, cost, and area.

XtractIM (11.0 Beta)

Improvements to XtractIM in the beta release which will follow the SpeedXP release:

• Broadband option license sharing ... With this release, XtractIM users will only take the broadband option license when the functionality is used.  This will give greater license access and flexibility to organizations with multiple XtractIM licenses.

XcitePI (5.0 Production)

Improvements to XcitePI in the most recent production release:

• Simplified user interface ... The XcitePI user interface takes on the check-list style flow approach of other Sigrity tools.  Enhancements are available for port selection and MCP connections.

• Increased capacity ... A hierarchical database supports additional performance and capacity in the GDS flow.

Unified Package Designer (11.0 Beta)

Improvements to UPD in the most recent beta release:

• Leadframe metal handling … Parametric definition of paddle and tie-bars combine with expanded editing options to streamline the flow and reduce the need of MCAD tools.

• Leadframe wirebond enhancements … Automatic placement of bondfingers along a guide independent of wirebond or die data.

• New high-speed design rule … The clearance of critical nets to pads on adjacent layers can now be easily checked.

Orbit IO (11.0 Beta)

Improvements to OrbitIO in the most recent beta release:

• Extended IOview capability … Automated and rule-driven  IO pad ring construction now includes PG and bump cell insertion as part of the OrbitIO pad ring option.

• Interface reuse … Easily export IO pad ring interfaces including bump and cell insertion.

• Enhanced RDL routing … New interactive editing capability is provided in the FC feasibility option.  Compaction functionality has also been added to maximize area available for PG mesh.

• Bump pattern construction … Flexible support for regular and asymmetrical multiple pitch patterns is included with the FC feasibility option.  This capability includes the ability to export appropriate bump views to IC and package design tools.

• Die shrink support … Die data can now be imported at drawn scale with a shrink value applied to represent final scale using the FC feasibility option.  Die related changes will export at the drawn scale while package related bump data will export at final scale.