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No Charge Training Class on SPEED2000

Focus: New capabilities in SPEED2000 for PCB layout signal integrity performance checks

Tuesday, Aptil 17 2012 (Register Here)

Up to now, there have been two primary methods for checking the electrical performance of PCB layouts. The first focuses on physical-rule based DRCs (design rule checks). The second approach relies on checks performed by time-domain simulations. The first approach does not ensure some of the most important electrical properties and cannot identify the impact if some DRC violations exist. This often leads to unnecessary over-design or inadequate under-design. The second approach can provide robust information if all the coupling between traces, vias and planes and non-ideal power and ground supplies are taken into account. But, the user time and computer resources required for board level time-domain simulation checks can make this approach impractical for time constrained product development flows. Newly released capabilities in SPEED2000 include easy to setup workflows, highly automated simulation and results processing and extensive graphic representations to help users assess layout electrical performance and identify potential design defects. The setup, simulation and results post-processing which could take days or weeks with conventional time domain simulation approaches can now be completed in minutes or hours. New capabilities in SPEED2000 include two customized flows for PCB layout checks: (1) the Trace Impedance/Coupling Checks, and (2) Signal Integrity Performance Metrics Checks.

Trace Impedance / Coupling Checks are used to quickly screen the board and present the following properties for trace connections from one device to another:

  • Number of vias, number of return path discontinuities, number of trace sections over voids, trace lengths;

  • Trace impedance and coupling coefficient summary table for sign-off;

  • Trace impedance and coupling coefficient with interactive results for debug, including detailed tables, collapsible and expandable plots, impedance and coupling coefficient values overlay with layout cross probing.

Signal Integrity Performance Metrics Checks perform electrical checks based on time-domain simulations that consider crosstalk and non-ideal power and ground supplies. An easy-to-use workflow combined with a high level of automation and parallel computing save users a huge amount of time to make checks on a large number of nets practical for complex real-world PCB projects. The results include:

  • Tx/Rx waveforms and worst case NEXT/FEXT waveforms;

  • SI performance metrics based on signal magnitudes, ISI (inter-symbol interference) and crosstalk at receivers;

  • Extensive checking reports.

        Note: This approach is profiled in a paper presented at DesignCon 2012:
        "Time Domain Electrical Design Checker of Printed Circuit Board Layout Design."

Trace Impedance / Coupling Checks provide a micro view of layout trace properties which are useful for design and debug. Signal Integrity Performance Metrics Checks  provide a macro view of overall SI performance which is useful for screening, review and sign-off. Used together, these checks provide great insight into layout SI performance.

The one day class will include instruction and hands-on exercises.

If you are interested in the topic and unable to attend, please email us at info@sigrity.com .










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