Sigrity looks forward to seeing you and your colleagues at the 49^th Design Automation Conference in San Francisco in a few weeks. We will be exhibiting in booth #2226.

     Sigrity DAC 2012 Update (download .pdf)

If you would like to arrange a meeting with Sigrity to cover topics of particular interest to you, we would love to make advance arrangements with you.  Please email us at Sigrity_DAC@sigrity.com.  You can also register here for pre-set time-slots with five topical presentations. Each of these presentations focuses on the vital importance of analyzing chips, packages and boards within an overall system context and the critical need to analyze signal- and power-integrity at the same time:

Chip IO Interconnect Modeling for System Success
(Power- & signal integrity applications)
 Monday, June 4 at 10:00 am - 11:00 am
 Tuesday, June 5 at 4:00 pm - 5:00 pm

IC Package Assessment and Extraction
(Influence of the package on system level characterization)
 Monday, June 4 at 11:00 am - 12:00 pm
 Tuesday, June 5 at 2:00 pm - 3:00 pm

System Level Checking and Extraction
(SI metrics, impedance and coupling assessment)
 Monday, June 4 at 1:00 pm - 2:00 pm
 Wednesday June 6 at 4:00 pm - 5:00 pm

Analyzing High-Speed Parallel Interfaces
(End-to-end DDR simulation)
 Monday, June 4 at 4:00 pm - 5:00 pm
 Wednesday, June 6 at 10:00 am - 11:00 am

SerDes Performance in an End-to-End System
(Utilizing IBIS AMI models in system level simulations)
 Tuesday, June 5  at 11:00 am - 12:00 pm
 Wednesday, June 6 at 1:00 pm - 2:00 pm

To sign-up

Please fill your registration information. Red fields are mandatory fields.