Meeting product introduction targets in today's climate necessitates concurrent strategies throughout the design process. Developing the chip-to-package net list concurrent with IO pad-ring construction during silicon design planning can shorten cycle-time while preventing over-design and its associated cost.

Identifying downstream connectivity issues in the early stages of design planning enable corrective measures when the options are greatest and cheapest to implement. Unfortunately limitations of traditional tools and methodologies make this an elusive goal leaving users to navigate multiple tools and databases to coordinate the chip-to-package net list.

This webinar will introduce the latest addition to the OrbitIO family of codesign tools - IC Net Planner. IC Net Planner delivers a task specific solution for pad-ring construction and chip-to-package net list planning in a low-cost product that can be incorporated into any flow while providing an attractive ROI. It builds on the familiar spreadsheet paradigm adding a powerful graphical environment that promotes rapid exploration of the solution space resulting in fewer iterations and shorter cycle-times. Domain specific outputs streamline data exchange to implementation tools helping expedite the design process.

The OrbitIO family of codesign tools reflects a revolutionary approach by providing a complete view of chip-package-board connectivity all within a unified design planning environment. This view combined with feasibility engines help anticipate and avoid downstream connectivity issues, enabling corrective measures while still in the early stage of design planning.

Webinar participants will be eligible for a special introductory price for the new capability.

	Participants will learn:
	Graphical pad-ring construction using LEF and spreadsheet data Use of virtual data to work-through incomplete design content How to process pad-ring updates and engineer changes On-the-fly parametric package construction or spreadsheet entry Perform automated chip-to-package connectivity assignment including differential signals How to generate placement and net list output using standard formats like DEF, AIF, or spreadsheets
	Who should attend?
	ASIC / Digital Design Engineers or Managers Pad Ring Designers or Codesign Specialists Package Design Engineers Engineers responsible for coordinating outsourced package design

Please provide us with the information below and we will get back to you to converge on a convenient Webinar time.