Sigrity at DesignCon 2009
We're looking forward to seeing you in early February.
If you're looking for additional information, please visit our main web site
at www.sigrity.com or contact us at firstname.lastname@example.org.
Sigrity DesignCon Booth Activities
We will be featuring recent advances relating to
existing Sigrity products and introducing
visitors to our newest product, Channel Designer™.
Booth Number: 613
Exhibit Hours: Tuesday and Wednesday, 12:30 pm - 6:30 pm
Drawing: Wednesday afternoon at 5:00 pm
Notable Papers and Panels
Tuesday, February 3
System IO Planning and Design Feasibility
- Challenges and Solutions ...Examination of trends driving coordinated system IO
planning and practical approaches that cross chip, package and board domains.
Time: 11:05 am - 11:45 am
Session Number: A-TA4
Author: Kevin Rinebold, Sigrity
TECHNICAL PANEL: High-Speed Channel
Designs ...Strategies for handling chip-to-chip serial link communication
to minimize jitter. The emergence of the IBIS Algorithmic Modeling Interface
(AMI) standard will also be discussed.
Time: 3:45 pm - 5:00 pm
Chairperson: Moises Cases, IBM
Mohammad Ali, Broadcom; Kumar Keshavan, Sigrity; Nam Pham, IBM; Lawrence
Williams, Ansoft; Dmitry Smolyansky,
Wednesday, February 4
Broadband Methodology for Power Distribution
System Analysis of Chip, Package and Board for High-Speed IO Design ...Characterization
utilizing frequency domain impedances to assess power delivery system coupling and the
impact this has on simultaneous switching effects for adjacent IO cells.
Time: 9:20 am - 10:00 am
Session Number: A-WA2
Authors: Hsing-Chou Hsu,
VIA Technologies; Chi-Hsing Hsu, Azurewave Technologies; Jack Lin,
Time and Frequency Analysis of Signal Noise as a Function of Power
Noise and Vice Versa of a Microcontroller (µC) Plus its Packaging (LQFP + PCB) ...Strategies
for the assessment of signal and power integrity effects in complex systems.
Simulations determine the impact of distributed on-chip and packaging decoupling capacitors.
Time: 11:05 am - 11:45 am
Session Number: 4-WA4
Miersch, EFM-Consulting; Mehmet Goekcen, Infineon; Thomas Steinecke,
The Effects of Chip and Board Behavior on Package-Centric,
System-Aware Power Delivery Design ...Chip and board electrical performance
is assessed for four packaging approaches.
Time: 2:50 pm - 3:30 pm
Session Number: 4-WP2
Virenda Adsure, Intel; Jiang Li, Sigrity; Long Wang, Intel
Thursday, February 5
Switching Voltage Regulator Noise
Coupling Analysis for Printed Circuit Board Systems ...Switching voltage regulator
noise is becoming an increasingly significant challenge for motherboard designers and
can lead to system reliability issues. A methodology is discussed to anticipate and
avoid issues before building boards.
Time: 10:40 am - 11:20 am
Session Number: 10-TH3
Authors: Amy Luoh, Intel;
Gene Garrison, Intel; Jon Powell, Intel
Complete DesignCon 2009 Schedule (link)