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Learn how you can maximize the power of Sigrity tools and create efficient modeling/simulation methodologies in your design flow. Industry experts will share their experiences with critical power delivery and signal integrity analysis at the chip, package and board level. Sigrity will present the highlights of recent major releases, popular application areas, tips, and upcoming new features.

Exchange your ideas and opinions in the lively Q&A session. Meet many of your peers who are also working at the frontier of challenging high-speed designs. So come on and join this technical social event. Just click on the registration link following the agenda and sign up to attend.

You must register by August 23, 2004 in order to reserve your seating for this event!


11:45 Registration/Lunch Buffet
12:50 Opening Remarks
Dr. Jiayuan Fang, President, Sigrity
1:00 Power Integrity Analysis for Die/Package/PCB Co-Design
Dr. Zhiping Yang, Senior Signal Integrity Engineer, Cisco Systems
2:00 Cool Tips
Ken Mohamed, Application Engineer, Sigrity
2:20 Break
2:35 High Speed DDR Performance in 4 vs. 6 Layer FCBGA Package Design
Dr. Edward Chan, nVIDIA
3:15 Sigrity Software Highlights
Sam Chitwood, Field Application Engineer, Sigrity
new features in recent releases
new applications - IR drop, high-speed signal net characterization, HSPICE co-sim
new IC power grid tool - XcitePI
4:15 Break
4:30 Sigrity Software Roadmap
Raymond Y. Chen, Vice President, Sigrity
4:50 Q&A
5:10 Door Prize Drawing

Register today seating is limited!



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  Modified: October 31, 2012

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